Source Decoder for Non-Volatile Memory Leakage Control
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Solution Overview
Problem
Existing address decoders for non-volatile memory arrays suffer from significant leakage currents in non-selected memory cells, particularly in large sector memory arrays with small MOS transistor dimensions, which affects electrical performance and manufacturing capabilities.
Innovation Solution
The introduction of a source-decoder stage in the address decoder, which biases source lines based on logic combinations of row-driving signals, reduces leakage currents by setting appropriate voltage values during memory operations, thereby improving electrical performance and allowing for larger sector dimensions and smaller transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MOS transistor dimensions are reduced to increase memory density, then manufacturing precision and area utilization improve, but leakage currents in non-selected cells increase significantly
Solution Approach 1:
The address decoder is segmented into two independent stages: a row decoder that selects word lines and a source decoder that selects source lines. This segmentation allows independent optimization of each stage, with the source decoder specifically designed to control leakage currents in non-selected cells while the row decoder maintains high-speed selection capability.
Solution Approach 2:
The source decoder acts as an intermediary control stage between the row decoder and the memory cells. It receives row-driving signals and generates controlled voltage values for source lines, mediating the control of MOS transistor gates to minimize leakage while maintaining selection functionality.
2Productivity
If sector size is increased to improve area utilization, then manufacturing efficiency improves, but leakage currents and electrical performance degradation worsen
Solution Approach 1:
The memory array is organized into multiple sectors with independent source line groups, each controlled by dedicated control logic in the source decoder. This allows selective activation of only the source lines corresponding to the currently accessed sector, minimizing leakage currents in non-selected sectors while maintaining large overall sector sizes for high area utilization.
3Device complexity
If conventional address decoder is used to simplify structure, then device complexity is reduced, but leakage control capability and electrical performance worsen
Solution Approach 1:
The source decoder merges multiple functions into a single control stage: it receives row-driving signals, performs logical operations to determine the currently selected word line, generates controlled voltage values for source line selection, and activates corresponding MOS transistors. This integration achieves comprehensive leakage control without proportionally increasing overall device complexity.
Solution Approach 2:
The source decoder dynamically adjusts source line voltages based on the current selection state. It continuously monitors row-driving signals and adapts the voltage values applied to source lines in real-time, enabling optimal leakage control that responds to changing access patterns while maintaining simple structural implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly minimizes leakage currents and enables the manufacturing of memory devices with improved electrical performance, allowing for larger sector sizes and optimized area utilization in non-volatile memory devices.
Implementation Method 1
This electric current, by the Joule effect, generates the temperatures required for phase change
Implementation Method 2
the address decoder is configured for applying voltage values to a control terminal of the MOS selection transistor
Data Source
AI summary
An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.