Differential Equalizer Resonant Circuits for High-Frequency ISI

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Solution Overview

Problem

Traditional differential equalizers struggle to effectively compensate for intersymbol interference (ISI) at higher frequencies in wireline communications, leading to significant eye jitter and unreliable clock and data recovery, due to limitations in their gain-frequency response and increased power consumption.

Innovation Solution

The implementation of equalizers with resonant circuits in source degeneration and feedback circuits, which tailor the gain-frequency response to better compensate for ISI, including series-connected primary and secondary equalizer stages with tunable resistors and capacitors, and LC resonant circuits to optimize gain and frequency performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional equalizers are used for lower-frequency transmissions, then ISI compensation is adequate at those frequencies, but they cannot adequately compensate for higher ISI inherent in increasingly higher frequency communications

Engineering Contradiction:
ImproveISI compensation capabilityVSAvoidfrequency range adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The equalizer employs adjustable gain stages with variable gain factors that can be dynamically tuned to match different frequency channel characteristics. The gain stages include adjustable amplifiers that can be configured through control signals to provide optimal equalization for both lower and higher frequency transmissions, making the equalizer adaptive to different frequency ranges rather than fixed for a single frequency band

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The equalizer changes its transfer function parameters by adjusting the gain factors of multiple gain stages. Each gain stage has a controllable gain factor that can be modified to alter the overall frequency response of the equalizer, enabling it to compensate for ISI at different frequency ranges by changing the gain parameters to match the specific channel loss characteristics

Inventive Principle:
Principle #35Parameter changes

2Reliability

If more gain stages are added to equalizers to tackle ISI issues at higher frequencies, then ISI compensation improves, but power consumption significantly increases

Engineering Contradiction:
ImproveISI compensation capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The equalizer uses a moderate number of gain stages (first, second, and third gain stages) rather than excessive stages, and each stage can be independently adjusted to provide just enough gain to compensate for ISI. The adjustable gain factors allow the equalizer to achieve adequate ISI compensation with fewer stages by optimizing the gain distribution across stages rather than adding more stages indiscriminately

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The equalizer optimizes power consumption by adjusting the gain parameters of each stage to provide only the necessary amplification needed for ISI compensation. The control signals that adjust gain factors can also control the activation and gain levels of each stage, allowing the system to use minimal power by activating only the necessary stages and setting appropriate gain levels rather than running all stages at maximum power

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If traditional equalizers are used, then circuit complexity is lower, but they produce significant eye jitter that makes clock and data recovery unreliable

Engineering Contradiction:
Improvecircuit complexityVSAvoidclock and data recovery reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The equalizer uses dynamically adjustable gain stages that can be tuned to optimize eye opening and reduce eye jitter for specific channel conditions. The adjustable gain factors allow the equalizer to adaptively compensate for frequency-dependent losses, thereby reducing eye jitter and improving clock and data recovery reliability without requiring overly complex circuit architectures

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The equalizer employs control signals that can be generated based on feedback from the received signal quality (such as eye diagram measurements or jitter measurements). This feedback mechanism allows the equalizer to automatically adjust its gain factors to optimize performance, reducing eye jitter and improving recovery reliability in a controlled manner that does not require excessive circuit complexity

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces eye jitter and enables robust data detection at higher frequencies, improving the receiver's ability to synchronize and recover data accurately while minimizing power consumption.

Implementation Method 1

equalizers with resonant circuits that enable the gain-frequency response of the equalizers to be tailored to more effectively compensate for intersymbol interference (ISI) over a bandwidth of interest

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentEP2456070B1Differential equalizers with source degeneration and feedback circuits
Publication Date: 2013.09.11 FREESCALE SEMICON INC
  • EP2456070B1 patent drawingFigure 1~2
  • EP2456070B1 patent drawingFigure 3
  • EP2456070B1 patent drawingFigure 4~6

AI summary

An embodiment of an equalizer (200) includes a voltage-to-current converter (310) and a current-to-voltage converter (350). The voltage-to-current converter (310) is configured to convert a differential input voltage to a differential current, and includes a differential amplifier with a first transistor (316) and a second transistor (318), and a first source degeneration circuit (320) coupled between the first transistor (316) and the second transistor (318). An embodiment of the first source degeneration circuit (320) includes a first resonant circuit (334). The current-to-voltage converter (350) is coupled to the voltage-to-current converter (310), and is configured to convert the differential current to a differential output voltage. The current-to-voltage converter (350) includes a first inverter with a first feedback circuit (364) and a second inverter coupled to the first inverter, which includes a second feedback circuit (366). An embodiment of the first feedback circuit (364) includes a second resonant circuit (380), and an embodiment of the second feedback circuit (366) includes a third resonant circuit (382).