Source-Degenerated Transconductance Amplifier for Linearity and CMRR
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Solution Overview
Problem
Prior art transconductance amplifiers face issues with low linearity and high common-mode gain due to large parasitic capacitance, which is exacerbated by the need for long channel lengths in NMOS transistors, and fail to effectively address common-mode rejection.
Innovation Solution
A transconductance amplifier design incorporating a source degeneration network with a parallel connection of MOS transistors and source resistors across specific nodes, allowing for high linearity and common-mode rejection without the need for long channel lengths, achieved through a balanced circuit configuration with negative feedback and proper biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If long channel length is used for NMOS transistors to improve linearity, then linearity is improved, but parasitic capacitance increases and speed deteriorates
Solution Approach 1:
The amplifier is divided into two independent differential pairs (first and second differential pairs), each handling one side of the differential signal. This segmentation allows each pair to be optimized independently, with short channel transistors for speed while maintaining linearity through the overall differential configuration and source degeneration network.
Solution Approach 2:
The invention changes the channel length parameter from long to short for the NMOS transistors, and compensates for the linearity requirement through other means: the source degeneration network with carefully selected resistor values and the differential configuration. This parameter change enables faster operation while maintaining acceptable linearity.
2Manufacturing precision
If long channel length is used for NMOS transistors to improve linearity, then linearity is improved, but parasitic capacitance increases
Solution Approach 1:
By segmenting the amplifier into two differential pairs with independent signal paths, the parasitic capacitance of each transistor is reduced (due to short channels), and the overall effect is managed through the differential configuration which rejects common-mode capacitance effects.
Solution Approach 2:
The source degeneration network provides negative feedback that linearizes the transfer characteristic of the short-channel transistors, compensating for the non-ideal behavior that would normally require long channels. This feedback mechanism reduces the need for long channel lengths and thus reduces parasitic capacitance.
3Device complexity
If conventional transconductance amplifier configuration is used, then circuit simplicity is maintained, but common-mode rejection is poor
Solution Approach 1:
The amplifier is segmented into two symmetric differential pairs with separate signal paths for in-phase and out-of-phase inputs. This segmentation enables the circuit to process differential signals while rejecting common-mode signals, improving common-mode rejection ratio without significantly increasing complexity.
Solution Approach 2:
The source degeneration network introduces asymmetric elements (resistors with different values) into the symmetric differential pair configuration. This controlled asymmetry allows the circuit to differentiate between differential and common-mode signals, improving common-mode rejection while maintaining reasonable complexity.
Data Source
AI summary
A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.