Source-Down Vertical Semiconductor Structure Using Gate Through-Vias
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Solution Overview
Problem
Conventional semiconductor devices and methods for forming semiconductor devices face issues such as excess cost, inadequate integration, decreased reliability, and relatively low performance due to limitations in scalability and process complexity, particularly in achieving a drain/gate up with source-down configuration.
Innovation Solution
A method and structure for semiconductor devices that utilize through-semiconductor vias to electrically connect gate electrodes on opposite sides of a semiconductor wafer, allowing for a source-down configuration with minimal additional masking steps, leveraging standard source-up fabrication flows and incorporating trench gate devices with shield electrodes and isolation structures to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor devices are used with standard fabrication flows, then manufacturing process is simple, but device configuration cannot achieve drain/gate up with source-down arrangement
Solution Approach 1:
The patent inverts the conventional source-up configuration to achieve source-down configuration by rotating the device 180 degrees. This inversion allows the source region to be positioned at the bottom while drain and gate remain at the top, enabling new device configurations without fundamentally changing the fabrication process
Solution Approach 2:
The patent uses standard source-up fabrication flows to create source-down devices, making the fabrication process universal. The same fabrication steps can produce both source-up and source-down configurations by simply rotating the wafer orientation, thus one process serves multiple device configuration purposes
2Reliability
If through-semiconductor vias are used to connect gate electrodes on opposite sides, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent introduces through-semiconductor vias as intermediary structures to connect gate electrodes on opposite sides of the wafer. These vias act as conductive pathways that enable electrical connection through the substrate, improving device performance by allowing gate control from both surfaces
Solution Approach 2:
The patent combines standard fabrication steps with through-via formation in an integrated process flow. By merging the via creation steps with existing fabrication sequences and using the same masking and etching infrastructure, the additional cost is minimized while achieving the electrical performance benefits
3Ease of manufacture
If minimal additional masking steps are used, then manufacturing cost is reduced, but alignment precision may be compromised
Solution Approach 1:
The patent performs preliminary alignment mark formation and pattern definition before the main fabrication steps. By pre-establishing reference markers and patterns on the wafer surface, subsequent masking and etching steps can be accurately aligned without requiring additional complex alignment procedures, thus maintaining precision while minimizing steps
Solution Approach 2:
The patent uses existing patterns and structures on the wafer as templates for subsequent fabrication steps. By copying established geometries and using self-aligned processes where possible, the need for additional masking steps is reduced while maintaining the precision of feature placement through the inherent alignment of the copying process
Data Source
AI summary
A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.