Source-Down Semiconductor Layout for Larger Active Area
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Solution Overview
Problem
Semiconductor devices face challenges in maximizing their active area and durability due to limitations in electrode configuration and bonding processes, which affect current rating and service life.
Innovation Solution
A semiconductor device with a source-down structure, where the source electrode is on the bottom surface, and a wire connects a region of the gate electrode to a pad on the chip's second surface, reducing the gate electrode pad area and increasing the active area, while using conductive materials and wire bonding to enhance durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode pad area is large to ensure electrical connection, then the connection reliability is improved, but the active area of the chip is reduced
Solution Approach 1:
The gate electrode is extended from the chip surface into the sealing resin in the vertical dimension, creating a three-dimensional structure. This allows the electrical connection to be established through wire bonding to the side surface of the gate electrode rather than requiring a large pad area on the chip surface, thus resolving the contradiction between connection reliability and active area.
Solution Approach 2:
The sealing resin serves as an intermediary medium that provides a mounting surface for the gate electrode. The gate electrode is embedded in the sealing resin and extends upward, allowing wire bonding to connect to the gate electrode's side surface. This intermediary structure enables reliable electrical connection without occupying chip surface area.
2Ease of manufacture
If conventional electrode configuration is used, then the manufacturing process is simple, but the active area is limited and current rating is reduced
Solution Approach 1:
The drain and source electrodes are positioned on opposite surfaces of the chip (drain on first surface, source on second surface), utilizing the vertical dimension. This three-dimensional electrode arrangement increases the effective current path area without complicating the manufacturing process, thereby improving current rating while maintaining manufacturing simplicity.
3Area of moving object
If wire bonding is used to connect gate electrode, then the active area is increased, but the bonding area must be minimized to improve durability against thermal stress
Solution Approach 1:
The wire bonding is extracted from the chip surface plane and relocated to the side surface of the gate electrode that protrudes into the sealing resin. This extraction allows the bonding area to be separated from the active chip area, enabling minimal bonding area for improved thermal stress durability while maintaining increased active area on the chip surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a larger active area, improved durability against thermal stress, and cost reduction by minimizing the bonding area and eliminating the need for costly processes like etching, thereby extending the component's service life.
Implementation Method 1
a wire connecting a first region of the gate electrode to a second region on the second surface of the chip
Data Source
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AI summary
According to one embodiment, there is provided a semiconductor device including a chip (1), a drain electrode (4) arranged on a first surface of the chip (1), a source electrode (2) arranged on a second surface provided on a back side of the first surface of the chip (1) and having a front surface on a device bottom surface, a gate electrode (3) having a front surface on the device bottom surface, and a wire (W) connecting a first region of the gate electrode (3) to a second region on the second surface of the chip (1).