Air-Gap Source/Drain Structure for Dense DRAM Speed Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As DRAM memory cell dimensions decrease to increase packing density, capacitive coupling leads to increased parasitic capacitance, reducing device speeds and overall performance.
Innovation Solution
A semiconductor device structure with air gaps between adjacent source/drain structures is implemented, reducing capacitance by forming fin structures, word lines, and source/drain structures with a contact etch stop layer to seal and surround the air gaps, thereby enhancing operational speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM memory cell dimensions are reduced to increase packing density, then packing density is improved, but parasitic capacitance increases due to capacitive coupling
Solution Approach 1:
An air gap is introduced as an intermediary space between adjacent source/drain structures. This air gap acts as a mediator that reduces capacitive coupling between the structures, thereby decreasing parasitic capacitance while allowing the structures to remain in close proximity for high packing density
Solution Approach 2:
The air gap is selectively positioned only between adjacent source/drain structures where capacitive coupling occurs, rather than throughout the entire device. This localized approach reduces parasitic capacitance at critical interfaces while maintaining overall device compactness and functionality
2Quantity of substance
If dimensions are reduced to increase packing density, then packing density is improved, but operation speed decreases due to increased parasitic capacitance
Solution Approach 1:
The air gap serves as an intermediary that electrically isolates adjacent source/drain structures, reducing parasitic capacitance and thereby improving operation speed without requiring increased spacing between structures
3Object-generated harmful factors
If air gaps are formed between source/drain structures, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The air gap is formed as part of the source/drain structure fabrication process itself, rather than as a separate post-processing step. The recessed regions are created during the epitaxial growth stage, and the air gaps are naturally formed when adjacent recessed regions do not merge, simplifying the overall manufacturing process
Data Source
AI summary
A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.