Source/Drain Air-Gap Structure for Lower Gate Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is reducing parasitic capacitance between source/drain features and gate while maintaining desired K value for devices as ICs scale down.
Innovation Solution
A semiconductor device structure is fabricated with a stack of semiconductor layers, including alternating first and second semiconductor layers with different etch selectivity and oxidation rates, forming fin structures and gate electrodes to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then productivity and cost efficiency are improved, but parasitic capacitance between source/drain features and gate increases
Solution Approach 1:
The patent introduces a vertical air gap dimension between the source/drain features and the gate, separating them in the vertical direction rather than maintaining only horizontal separation. This vertical separation effectively reduces parasitic capacitance while allowing continued scaling in the horizontal plane, thus maintaining productivity improvements from geometry reduction.
Solution Approach 2:
The patent introduces an intermediary layer (insulator layer with air gap) between the source/drain features and the gate. This intermediary structure acts as a capacitor with very low capacitance, effectively reducing the parasitic capacitance between the source/drain and gate while allowing them to remain in close proximity for continued scaling.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved, but device performance (K value) becomes difficult to maintain
Solution Approach 1:
By introducing vertical separation through an air gap, the patent reduces parasitic capacitance that would otherwise degrade device performance. This allows continued horizontal scaling for improved productivity while maintaining K value through the vertical dimension control.
Solution Approach 2:
The patent changes the dielectric parameter between source/drain and gate by introducing an air gap (extremely low dielectric constant) in the vertical direction. This parameter change reduces parasitic capacitance effects, allowing device performance to be maintained even as geometry dimensions are reduced for increased productivity.
3Area of moving object
If source/drain features are placed closer to gate to maintain device scaling, then functional density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent resolves the contradiction by separating source/drain from gate in the vertical dimension while maintaining close horizontal proximity. This allows maximum chip area utilization through continued scaling while the vertical air gap prevents parasitic capacitance increase.
Solution Approach 2:
An insulator layer containing an air gap is introduced as an intermediary between source/drain features and the gate. This intermediary structure enables close horizontal spacing for area efficiency while the vertical air gap component provides electrical isolation to prevent parasitic capacitance increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively reduces parasitic capacitance and maintains desired K value, enhancing device performance and efficiency.
Implementation Method 1
alternating first and second semiconductor layers with different etch selectivity
Implementation Method 2
different etch selectivity and oxidation rates
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate between two adjacent semiconductor layers, a supporting layer disposed between the S/D feature and the substrate, the supporting layer having a curved top surface, a dielectric spacer disposed between and in contact with one of the semiconductor layers and the substrate, wherein the dielectric spacer, the substrate, the supporting layer, and a bottom surface of the S/D feature define an air gap therein.