Source/Drain Contact Dielectric Stack for Air Gap Sealing

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Solution Overview

Problem

The ion implantation process used to seal air gaps in the interlayer dielectric (ILD) of semiconductor devices can cause damage to epitaxial materials of source/drain regions and channel regions, despite serving as an implantation energy absorption layer.

Innovation Solution

A reduced energy/dosage ion implantation process is employed to seal the air gaps, accompanied by a thinner implantation energy absorption dielectric layer over the ILD. Additionally, a multi-layer dielectric film is deposited to ensure the formed source/drain vias and gate contacts have an acceptable height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation process is used to seal air gaps in the interlayer dielectric, then the air gaps are effectively sealed, but damage is caused to the epitaxial materials of source/drain regions and channel regions

Engineering Contradiction:
Improveair gap sealingVSAvoiddamage to epitaxial materials
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the dielectric layer into multiple segments: a first dielectric layer containing air gaps that need sealing, and a second dielectric layer deposited over it. The ion implantation is applied selectively to seal air gaps in the first layer while the second layer protects underlying epitaxial materials from damage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary deposition of the second dielectric layer over the first dielectric layer before conducting ion implantation. This preliminary action creates a protective barrier that prevents ion damage to epitaxial materials while still allowing the implantation process to seal air gaps in the first layer.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If a thicker implantation energy absorption dielectric layer is used to protect epitaxial materials, then damage to source/drain regions is reduced, but the height of source/drain vias and gate contacts becomes unacceptable

Engineering Contradiction:
Improvedamage to source/drain regionsVSAvoidheight of source/drain vias and gate contacts
Core Design Contradiction:
Object-affected harmful factorsVSLength of moving object

Solution Approach 1:

The patent segments the dielectric structure into a first dielectric layer (with air gaps) and a second dielectric layer (deposited over it). This segmentation allows the first layer to be relatively thin for via access while the combined structure provides sufficient protection, resolving the contradiction between protection thickness and via height requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of the dielectric layers, specifically controlling the thickness of the first dielectric layer to be sufficient for air gap sealing but not excessive, and depositing a second dielectric layer to provide additional protection. This parameter optimization ensures both protection of epitaxial materials and acceptable via heights.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes damage to the epitaxial materials and channel regions while effectively sealing the air gaps, thereby maintaining device performance and integrity.

Implementation Method 1

the implantation process causes the interlayer dielectric layer to expand and seal the air gap

Methodology Applied
Scientific EffectDielectric expansion:

Data Source

PatentUS20250126874A1Semiconductor device and manufacturing method thereof
Publication Date: 2025.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250126874A1 patent drawing
  • US20250126874A1 patent drawing
  • US20250126874A1 patent drawing

AI summary

A method includes a number of operations. An interlayer dielectric (ILD) layer is formed over a source/drain region on a substrate. A source/drain contact extending through the ILD layer to electrically connect with the source/drain region is formed. An air gap extending through the ILD layer is formed. An implantation energy absorption dielectric layer is formed over the ILD layer. An implantation process is performed on the implantation energy absorption dielectric layer, wherein the implantation process causes the ILD layer expands to seal the air gap. A first implant-free dielectric layer is formed over the implantation energy absorption dielectric layer. A second implant-free dielectric layer is formed over the first implant-free dielectric layer. A source/drain via extending through the second implant-free dielectric layer, the first implant-free dielectric layer, and the implantation energy absorption dielectric layer to the source/drain contact is formed.