Source/Drain Backside Conductive Paths for Dense Chip Routing
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Solution Overview
Problem
As semiconductor device size shrinks, there is a need for improved architectures for power rail and signal routing to increase integration density, particularly in achieving flexible and efficient connections between front side and backside metal layers.
Innovation Solution
The implementation of a front side to backside conductive path through source/drain features in semiconductor devices, allowing for flexible routing and connections, including local connections, backside signal connections, and power rail connections, by forming conductive paths through source/drain features in standard or filler transistor cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional front-side only routing is used, then manufacturing process is simple, but integration density cannot be sufficiently increased
Solution Approach 1:
The patent transitions from two-dimensional front-side routing to three-dimensional routing by extending conductive paths through the substrate to the backside. This dimensional change allows power rails and signal lines to be routed on both surfaces of the device, effectively doubling the available routing space and enabling higher integration density without increasing planar footprint.
Solution Approach 2:
The routing architecture is segmented into front-side and back-side components, with each side handling specific routing functions. Power rails are routed on the front side while signal connections are routed on the back side, dividing the routing tasks to reduce interference and improve manufacturability while achieving high integration density.
2Area of moving object
If minimum feature size is reduced to increase integration density, then more components fit in given area, but power rail and signal routing architectures need continuous improvement
Solution Approach 1:
By utilizing the third dimension (substrate thickness) to route power rails on the front side and signal lines on the back side, the patent provides separate routing planes that do not interfere with each other. This allows continued scaling of minimum feature size while maintaining routing simplicity and achieving higher component density in the given chip area.
3Adaptability or versatility
If front side to backside conductive paths are implemented, then flexible routing and space utilization are improved, but manufacturing process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct front-side processing steps and back-side processing steps. Front-side power rail formation is completed before substrate thinning and backside processing, allowing each side to be manufactured independently with standard CMOS techniques, thereby reducing overall process complexity despite the three-dimensional routing capability.
Data Source
AI summary
Embodiments of the present disclosure provide semiconductor devices having a front side to backside conductive path through a source/drain feature. In some embodiments, the front side to backside conductive path may be formed through a source/drain feature in a standard cell. The other embodiments, the front side to backside conductive path is formed through a source/drain feature in a filler cell. The front side to backside conductive path enables flexible routing for local connections, backside signal connections, and/or backside power rail connection.