Multilayer Source/Drain Barrier Layers for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining device performance and integration density, including increased stray capacitances and resistance.
Innovation Solution
The formation of multilayer source/drain regions with embedded barrier layers, which are grown epitaxially in a bottom-up process, reduces junction capacitances and improves overall device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but stray capacitances and resistance increase
Solution Approach 1:
The source/drain region is segmented into multiple layers with alternating semiconductor and barrier materials, creating a multilayer structure. This segmentation allows the barrier layers to be distributed throughout the source/drain region, effectively reducing stray capacitances between the source/drain and channel while maintaining low resistance pathways through the semiconductor layers.
Solution Approach 2:
Different materials are used at different locations within the source/drain region. Barrier materials with high dielectric constant are placed in specific layers to reduce capacitance, while highly doped semiconductor materials are placed in other layers to maintain low resistance. This local differentiation of material properties optimizes both capacitance reduction and resistance management.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but resistance increases
Solution Approach 1:
The source/drain region is divided into multiple semiconductor layers separated by barrier layers. Each semiconductor layer can be independently doped to create highly conductive pathways, while the segmented structure prevents excessive resistance accumulation that would occur in a single continuous doped region at scaled dimensions.
Solution Approach 2:
The source/drain region uses a composite structure combining multiple semiconductor materials and barrier materials. Highly doped semiconductor layers provide low resistance pathways, while barrier layers with appropriate electrical properties reduce capacitance. This composite approach allows simultaneous optimization of resistance and capacitance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of epitaxially grown barrier layers within the multilayer source/drain regions effectively reduces stray capacitances, enhancing the output resistance performance and maintaining integration density.
Implementation Method 1
depositing a barrier layer at a bottom of the opening, wherein after the depositing the barrier layer a top level of the barrier layer is below a bottom of the multilayer stack
Implementation Method 2
forming a multilayer source/drain region over the barrier layer by depositing a first semiconductor material over the barrier layer
Data Source
AI summary
Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.