Source/Drain Contact Layout Below Gate Stack for Compact Interconnects
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Solution Overview
Problem
As semiconductor process technology continues to scale down, process variations have become more challenging in the manufacturing of integrated circuits (ICs), particularly in the implementation of gate vias in active regions of semiconductor devices.
Innovation Solution
The semiconductor structure includes a first and second active region on a substrate, with gate structures and gate vias arranged correspondingly. A local interconnect is arranged over a non-active region to connect source/drain contacts across the active regions, following specific guidelines related to the arrangement of gate vias and separation spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If source/drain contacts are formed at the same level as gate structures, then electrical connection is achieved, but device area increases and manufacturing precision becomes more difficult
Solution Approach 1:
The source/drain contacts are positioned at a different height level than the gate structures, specifically below the gate stack level. This vertical dimensional change allows the contacts to be formed in lower-lying regions while the gate structures occupy higher regions, achieving electrical connection without requiring the contacts to be at the same planar level as the gates, thereby reducing device area and simplifying alignment requirements
2Reliability
If more connectors are used to connect source/drain contacts across active regions, then electrical connection reliability improves, but device complexity and area increase
Solution Approach 1:
The gate structures are configured to extend continuously over both the first and second active regions, serving a dual function: providing gate control for the transistor channel and simultaneously acting as interconnect structures that bridge the source/drain contacts across the active regions. This merging of gate and interconnect functions reduces the need for separate high-level connectors, simplifying the overall device structure while maintaining reliable electrical connections
Data Source
AI summary
A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.