Semiconductor Source/Drain Blocking Structure for Scaled MOSFET Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical and reliability characteristics.
Innovation Solution
The semiconductor device includes a substrate with specific patterns and structures, such as active patterns, source/drain patterns, blocking patterns, and gate electrodes, designed to enhance electrical and reliability characteristics through optimized dimensions and material compositions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically-stacked channel structures. Multiple channel patterns are stacked vertically to form a 3D configuration, enabling continued scaling and density improvement while maintaining adequate channel control and operational characteristics through the vertical dimension
Solution Approach 2:
The channel region is divided into multiple discrete channel patterns stacked vertically, with each channel pattern forming a separate conduction path. This segmentation allows independent optimization of each channel while achieving high integration density through vertical stacking, resolving the contradiction between miniaturization and operational performance
2Reliability
If the width of the blocking pattern is increased to prevent short circuits, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The blocking pattern width in the horizontal plane is reduced, compensating for the increased vertical dimension. By extending the blocking function vertically across multiple channel patterns, the horizontal footprint is minimized, reducing manufacturing precision requirements while maintaining effective short circuit prevention
Solution Approach 2:
The blocking pattern dimensions are optimized by changing from horizontal extension to vertical extension. The blocking pattern covers the vertical stack height rather than extending horizontally, allowing relaxed horizontal dimension control while maintaining blocking effectiveness against short circuits
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, a source/drain pattern on the substrate, and a blocking pattern between the active pattern and the source/drain pattern. A top surface of the blocking pattern may be in contact with a bottom surface of the source/drain pattern. The bottom surface of the source/drain pattern may have a first width in a first direction, and the top surface of the blocking pattern may have a second width in the first direction. The second width may be larger than the first width.