Source/Drain Bottle-Neck Recess for Low-Leakage SiGe Epitaxy
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Solution Overview
Problem
Traditional isotropic/v-shaped recesses in semiconductor substrates are not suitable for devices below 32 angstroms, leading to poor device performance due to issues like poor junction leakage and severe Si pullback after SiGe epitaxy growth, and high cutout in lightly doped drains.
Innovation Solution
A method involving biased dry etching to form bottle-neck shaped recesses in silicon substrates, followed by non-biased etching and epi-growing semiconductor material in these recesses, using gases like HeO2 and HBr, and potentially N2, to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional isotropic/v-shaped recesses are formed in the substrate, then the fabrication process is simple, but device performance deteriorates due to poor junction leakage and severe Si pullback
Solution Approach 1:
The etching process is divided into multiple stages: a first biased dry etching process to form an initial recess, followed by a second biased dry etching process to create the bottle-neck shape. This segmentation allows each etching step to be optimized independently, achieving both manufacturability and device performance.
Solution Approach 2:
The etching process transitions from a biased dry etching mode to a non-biased etching mode during fabrication. This dynamic adjustment of etching conditions enables the formation of the complex bottle-neck shape that improves device performance while maintaining process feasibility.
2Ease of manufacture
If traditional recess shapes are used, then manufacturing is easier, but junction leakage performance and Si pullback control worsen
Solution Approach 1:
The bottle-neck shaped recess creates different geometries at different locations: a wider opening at the top and a narrower section at the bottom. This local variation in geometry provides precise control over junction leakage performance and Si pullback while remaining manufacturable through staged etching processes.
Solution Approach 2:
The etching process parameters are changed between stages - using biased dry etching conditions for the initial recess formation, then transitioning to non-biased etching to achieve the final bottle-neck shape. These parameter changes enable precise control of recess geometry for improved junction characteristics.
3Device complexity
If LDD is formed at the substrate surface under the gate, then device structure is complete, but cutout becomes high
Solution Approach 1:
The bottle-neck shaped recess is formed preliminarily before LDD formation to prevent high cutout. The narrowed lower section of the recess acts as a barrier that prevents excessive LDD material from reaching critical regions, thereby preventing cutout issues while maintaining complete device structure.
Solution Approach 2:
The bottle-neck geometry acts as an intermediary structure between the gate and the LDD region. The narrowed section serves as a physical mediator that controls the interaction between these components, preventing direct contact that would cause high cutout while allowing the device structure to remain complete.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing drain induced barrier lowering, enhancing junction leakage, and improving SiGe epitaxy growth outcomes, resulting in better resistance and field mobility.
Implementation Method 1
performing a biased dry etching process to the substrate to remove a portion of the silicon substrate
Implementation Method 2
performing a biased dry etching process including adding HeO2 gas and/or HBr gas
Implementation Method 3
performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region
Implementation Method 4
epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate
Implementation Method 5
performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region
Data Source
AI summary
A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.