Source/Drain Buffer Layer Curvature for Leakage and Fault Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and performance due to issues such as stacking faults and leakage currents, which affect the integration density and functionality of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a source/drain pattern with a buffer layer, an intermediate layer, and a main layer, where the buffer layer covers the inner sides of the recess and has curved surfaces, and the intermediate layer is positioned between the buffer and main layers, helping to prevent stacking faults and reduce leakage currents by ensuring proper filling of the recess.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source/drain pattern with buffer layer and curved surfaces is used, then stacking faults are prevented and leakage currents are reduced, but device complexity increases
Solution Approach 1:
The buffer layer is formed in advance before the main source/drain layer, creating a preparatory structure that prevents stacking faults during subsequent fabrication processes. The curved surfaces are formed preliminarily to guide proper material deposition and prevent structural defects.
Solution Approach 2:
The buffer layer acts as an intermediary between the substrate and the main source/drain layer, mediating the interface to prevent stacking faults. The intermediate layer serves as a mediator between the buffer layer and main layer, ensuring proper structural transition and preventing leakage currents.
2Reliability
If the buffer layer has curved surfaces convexly curved toward the gate electrode, then leakage currents are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The buffer layer is designed with curved surfaces that are convexly curved toward the gate electrode, replacing flat surfaces with curved geometry to reduce leakage currents by improving electric field distribution and preventing charge accumulation at sharp corners.
3Manufacturing precision
If the intermediate layer is added between buffer layer and main layer, then proper filling of recess is ensured, but device complexity increases
Solution Approach 1:
The source/drain structure is segmented into multiple distinct layers: buffer layer, intermediate layer, and main layer. This segmentation allows each layer to perform its specific function independently, ensuring proper filling of the recess while maintaining manufacturing control.
4Productivity
If integration density is increased, then device performance is improved, but stacking faults and leakage currents increase
Solution Approach 1:
The buffer and intermediate layers are formed in advance to establish a defect-resistant structure before high-density integration, preventing stacking faults from occurring during subsequent processing steps.
Solution Approach 2:
The intermediate layer acts as a mediator between the buffer and main layers, ensuring proper structural transition and preventing leakage currents that would otherwise increase with higher integration density.
Data Source
AI summary
A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.