Source/Drain Epitaxial Cap Structure for Low-Resistance Nanosheet Contacts
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Solution Overview
Problem
As semiconductor devices shrink, the challenge of maintaining device performance and efficiency while scaling down poses difficulties in manufacturing, particularly in forming nanosheet channels and achieving effective gate-all-around transistor structures.
Innovation Solution
The process involves forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, using photolithography and self-aligned processes to create fin structures, and then patterning gate-all-around transistor structures with sacrificial layers and spacers, followed by epitaxial growth of source/drain features and cap layers to enhance conductivity and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase functional density, then production efficiency and cost are improved, but manufacturing precision and device performance deteriorate
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional nanosheet channels and gate-all-around structures. By stacking multiple semiconductor layers vertically to form nanosheets and surrounding them with gate electrodes on all sides, the device achieves higher functional density in the vertical dimension while maintaining manufacturability through self-aligned processes that ensure precise positioning despite scaling.
Solution Approach 2:
The patent divides the semiconductor structure into alternating layers of different materials (e.g., silicon and silicon germanium) with distinct etch selectivities. This segmentation enables selective removal of sacrificial layers to form nanosheet channels, allowing precise control of channel formation and gate positioning while maintaining overall device performance during scaling.
2Productivity
If nanosheet channels are formed to increase device density, then functional density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms complete stacks of alternating semiconductor layers before any channel or gate formation steps. These pre-formed stacks with built-in sacrificial layers serve as templates that guide subsequent self-aligned processes, eliminating the need for complex alignment steps and reducing manufacturing complexity despite the three-dimensional nanosheet structure.
Solution Approach 2:
The patent employs self-aligned processes where previously formed structures automatically position subsequent features. For example, the sacrificial layers within the stacked structure automatically define the positions of nanosheet channels and gate electrodes, eliminating the need for separate alignment operations and simplifying the manufacturing process.
3Reliability
If gate-all-around transistor structures are created to improve carrier mobility, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces sacrificial layers as intermediary structures that temporarily occupy the space where nanosheet channels will eventually form. These sacrificial layers are integrated within the stacked semiconductor structure and automatically position the gates in correct locations, achieving high manufacturing precision without requiring complex alignment procedures.
Solution Approach 2:
The gate-all-around structures are formed by first creating complete stacks with embedded sacrificial layers, then selectively removing these sacrificial layers to form nanosheet channels. This preliminary formation of the stacked structure with built-in positioning features ensures precise gate positioning is achieved automatically through self-aligned processes rather than requiring high-precision positioning operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density, high-performance nanosheet transistors with improved carrier mobility and drive current, effectively addressing the scaling challenges and enhancing manufacturing efficiency.
Implementation Method 1
the dopants in the source/drain cap layer are diffused and accumulated at and/or near an interface defined by the third epitaxial layer and the source/drain cap layer
Implementation Method 2
the source/drain cap layer reacts with the silicide layer
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.