Source/Drain Contact Profile Using ALE to Lower Contact Resistance
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Solution Overview
Problem
As semiconductor device dimensions shrink, the contact resistance between epitaxial source/drain regions and source/drain contact features increases, leading to performance degradation.
Innovation Solution
A method involving the formation of a fin structure over a substrate, followed by the creation of sacrificial gate structures and sidewall spacers, epitaxial growth of source/drain regions, and the use of atomic layer etching (ALE) processes to form self-aligned contacts, which reduces contact resistance by optimizing the contact area and material removal precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimension is reduced, then device integration density is improved, but contact resistance between source/drain contact features and epitaxial source/drain regions increases
Solution Approach 1:
The patent transitions from planar contacts to vertically extending contacts that penetrate through the gate structure. This dimensional change allows the contact to reach the epitaxial source/drain regions directly beneath the gate, maintaining low contact resistance even as lateral device dimensions are reduced for higher integration density.
Solution Approach 2:
The patent introduces a gate structure as an intermediary element that the contact penetrates through. This gate structure serves as a mediator that allows the contact to reach the underlying epitaxial source/drain regions while maintaining proper device architecture and electrical isolation between adjacent devices.
2Length of moving object
If contact area is reduced to accommodate smaller device dimensions, then device scaling is improved, but contact resistance increases
Solution Approach 1:
The patent compensates for reduced lateral contact area by extending the contact vertically through the gate structure. This creates a three-dimensional contact path that maintains sufficient contact area with the epitaxial source/drain regions despite reduced lateral device dimensions, enabling continued scaling without contact resistance penalties.
Solution Approach 2:
The patent changes the contact geometry from a two-dimensional planar interface to a three-dimensional vertical penetration. This parameter change in contact architecture allows the contact to maintain effective electrical connection through increased vertical interaction with the epitaxial source/drain regions, compensating for reduced lateral dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces contact resistance, enhancing the performance of semiconductor devices by improving the contact area and material etching precision, thereby supporting smaller device dimensions without compromising functionality.
Implementation Method 1
a method involving the formation of a fin structure over a substrate, followed by the creation of sacrificial gate structures and sidewall spacers, epitaxial growth of source/drain regions, and the use of atomic layer etching (ALE) processes to form self-aligned contacts
Implementation Method 2
epitaxial growth of source/drain regions
Data Source
AI summary
Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.