Source/Drain Contact Structure for Reduced Parasitic Capacitance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As integrated circuit technologies progress towards smaller technology nodes, parasitic capacitance associated with source/drain contacts becomes a significant issue affecting the overall performance of IC devices, as existing source/drain contacts are inadequate in reducing this capacitance.

Innovation Solution

A method is introduced to reduce parasitic capacitance by refilling a lower portion of the source/drain opening with a dielectric structure and forming a source/drain contact on the dielectric structure, thereby reducing the depth of the source/drain contact and minimizing the overlap area with adjacent features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If source/drain contact depth is increased to maintain electrical connection, then contact reliability is improved, but parasitic capacitance increases

Engineering Contradiction:
Improvecontact reliabilityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The source/drain contact structure is segmented into multiple portions with different depths. The first contact portion extends to a first depth while the second contact portion extends to a second depth that is greater than the first depth. This segmentation allows the contact to maintain reliability through adequate depth while reducing parasitic capacitance by varying the depth profile rather than uniformly increasing depth throughout.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the source/drain contact are given different local qualities in terms of depth. The first contact portion has a shallower depth while the second contact portion has a greater depth. This local variation in depth quality allows the contact to achieve both reliability (through sufficient depth in critical areas) and reduced parasitic capacitance (through reduced depth in other areas).

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250374652A1Semiconductor structures with reduced parasitic capacitance
Publication Date: 2025.12.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250374652A1 patent drawing
  • US20250374652A1 patent drawing
  • US20250374652A1 patent drawing

AI summary

In an embodiment, an exemplary method includes forming a dielectric structure over a substrate, the dielectric structure includes a first portion disposed between a first source/drain feature and a second source/drain feature adjacent to the first source/drain feature and a second portion over the first portion. The exemplary method also includes replacing a part of the first portion of the dielectric structure with a dielectric feature having a different composition than the dielectric structure, and replacing a part of the second portion of the dielectric structure with a source/drain contact electrically coupled to both the first and second source/drain features.