Source/Drain Contact Profile to Cut Gate Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, short channel effects prevent further scaling down of planar field effect transistors, and multi-gate devices introduce increased parasitic resistance and capacitance due to thin dielectric layers between conductive structures, leading to performance issues.
Innovation Solution
A method for forming source/drain contacts that do not extend below the bottommost level of the gate structure, reducing the depth of the source/drain contact to minimize parasitic capacitance between the source/drain contact and the adjacent gate structure, achieved through a series of etch processes and dielectric layer management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dielectric layers between gate structure and source/drain contact are made thinner to reduce device dimensions, then device scaling is improved, but parasitic capacitance between gate structure and source/drain contact increases
Solution Approach 1:
The patent controls the vertical depth of the source/drain contact to terminate above the bottommost level of the gate structure, using dimensional control in the depth direction to reduce parasitic capacitance while maintaining horizontal device scaling
Solution Approach 2:
The patent changes the depth parameter of the source/drain contact from extending to or below the gate bottom level to terminating above it, thereby reducing the overlapping area and parasitic capacitance between the source/drain contact and gate structure
2Ease of manufacture
If over-etching is performed to form source/drain contact opening extending into isolation feature, then contact formation is simplified, but lateral overlap between source/drain contact and gate structure increases causing increased parasitic capacitance
Solution Approach 1:
The patent applies different etch selectivities to different regions: using high selectivity to the gate structure to prevent lateral overlap and reduce parasitic capacitance, while still achieving adequate contact formation to the source/drain region
Data Source
AI summary
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.