Source/Drain Contact Depth Layout for Lower Gate Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices shrink in size, short channel effects prevent further scaling down of planar field effect transistors, and multi-gate devices introduce increased parasitic resistance and capacitance due to thin dielectric layers between conductive structures, leading to performance issues.
Innovation Solution
A method for forming source/drain contacts that do not extend below the bottommost level of the gate structure, reducing the depth of the source/drain contact to minimize parasitic capacitance between the source/drain contact and the adjacent gate structure, achieved through a series of etch processes and dielectric layer management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are used to improve gate control and reduce short-channel effects, then device performance is improved, but parasitic capacitance increases due to thin dielectric layers
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance by preventing the source/drain contact from extending under the gate structure. The contact opening is deliberately stopped at the gate bottom surface, eliminating the overlapping region that would create parasitic capacitance between the source/drain contact and gate electrode.
Solution Approach 2:
The patent controls the vertical depth of the source/drain contact opening to match the gate structure height, thereby eliminating the lateral overlap dimension. By making the contact depth equal to the gate height, the contact and gate are positioned at the same vertical level without overlapping, reducing parasitic capacitance in the lateral dimension.
2Ease of manufacture
If source/drain contact opening extends deep into isolation feature, then contact formation is achieved, but parasitic capacitance between source/drain contact and gate structure increases
Solution Approach 1:
The patent applies preliminary action by forming the gate structure to a specific height before creating the source/drain contact opening. The contact opening depth is pre-determined to match the gate height, ensuring that the contact will not extend beyond the gate bottom surface. This preliminary depth control prevents parasitic capacitance formation before the contact filling process occurs.
Solution Approach 2:
The patent changes the depth parameter of the source/drain contact opening to be equal to the gate structure height. By controlling the etch depth to precisely match the gate height, the contact opening stops at the gate bottom surface, eliminating the harmful lateral overlap and associated parasitic capacitance while maintaining adequate contact formation.
3Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then manufacturing cost is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the source/drain contact opening depth control with the existing gate structure formation process. By using the gate structure itself as the depth reference and stopping the etch at the gate bottom surface, the contact depth is automatically controlled without requiring separate depth measurement or additional alignment steps, simplifying the overall manufacturing process.
Solution Approach 2:
The gate structure serves as its own depth reference for the source/drain contact opening. The etch process automatically stops at the gate bottom surface using the gate structure as a physical barrier and reference, eliminating the need for external depth control mechanisms or additional process steps to ensure proper contact depth.
Data Source
AI summary
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.