Source/Drain Contact Structure With Built-In Extension for Lower Resistance
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Solution Overview
Problem
Current methods for forming device-level contacts in semiconductor devices, such as field-effect transistors, are complex, increase processing costs, and introduce additional barrier layer interfaces that limit device performance by requiring separate processes for forming source/drain contact extensions and contacts, which also increase contact resistance.
Innovation Solution
A method for forming source/drain contacts with integrated extensions by simultaneously depositing conductive material to create a built-in extension feature that connects adjacent contacts, reducing the need for separate processes and minimizing additional barrier layer interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used for forming source/drain contact extensions and contacts, then the fabrication process is more controllable, but the processing complexity and costs increase
Solution Approach 1:
The patent combines the formation of source/drain contact extensions and contacts into a single integrated process step. Conductive material is deposited to form both the extensions and the contacts simultaneously, eliminating the need for separate patterning and deposition steps that would otherwise be required. This merging reduces processing complexity while maintaining fabrication controllability through a unified process design.
2Manufacturing precision
If separate processes are used for forming source/drain contact extensions and contacts, then the fabrication process is more controllable, but processing costs increase
Solution Approach 1:
The patent merges the formation of source/drain contact extensions and contacts into a single process step, reducing the number of fabrication steps required. This integration decreases processing costs by eliminating redundant deposition and patterning operations while maintaining manufacturing precision through a unified process approach that ensures consistent material properties and interface quality.
3Manufacturing precision
If separate processes are used for forming source/drain contact extensions and contacts, then the fabrication process is more controllable, but additional barrier layer interfaces are introduced that limit device performance
Solution Approach 1:
The patent combines the formation of source/drain contact extensions and contacts into a single continuous conductive material deposition process. This approach eliminates the need for separate barrier layers at the interface between extensions and contacts, thereby reducing the number of interface layers that could limit device performance. The unified structure ensures direct electrical continuity while maintaining fabrication controllability through a single process parameter set.
4Manufacturing precision
If separate processes are used for forming source/drain contact extensions and contacts, then the fabrication process is more controllable, but contact resistance increases
Solution Approach 1:
The patent integrates the formation of source/drain contact extensions and contacts into a single deposition process, creating a continuous conductive material structure without intervening barrier layers. This unified approach minimizes contact resistance by ensuring direct electrical pathways between the extensions and contacts, while fabrication controllability is maintained through a single process that allows for optimized material composition and deposition parameters across the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces processing complexity and costs, and enhances device performance by minimizing contact resistance and enlarging the processing window for subsequent patterning processes.
Implementation Method 1
simultaneously depositing conductive material to create a built-in extension feature
Data Source
AI summary
A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and a conductive feature disposed in the ILD layer and electrically coupled to the first epitaxial S/D feature and the second epitaxial S/D feature. The conductive feature includes first portions having bottom surfaces contacting the first and the second epitaxial S/D features, and a second portion having a bottom surface contacting the ILD layer. The bottom surface of the second portion is above the bottom surface of the first portions.