Source/Drain Contact Structure for Lower-Resistance GAA Transistors
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Solution Overview
Problem
Existing fabrication techniques for gate-all-around and fork-sheet transistors face challenges in forming source/drain contacts with high resistance and manufacturing complexity, leading to performance bottlenecks and practicality issues.
Innovation Solution
The development of source/drain regions with semiconductor portions and contact metals that enhance contact area and reduce external resistance without significant manufacturing complexity, using epitaxial nubs and stress-inducing contact metals to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If deep etch techniques are used to form source/drain contacts in gate-all-around transistors, then contact area is increased, but manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The patent applies preliminary action by forming the source/drain regions through epitaxial growth before the gate structure is completely formed. This allows the contact area to be established early in the process when the structure is more accessible, avoiding the need for deep etching later. The epitaxial nubs are grown to the desired height and area before gate material deposition, pre-positioning the contact regions to reduce subsequent process complexity.
Solution Approach 2:
The patent transitions from planar contact formation to vertical contact formation by growing epitaxial nubs with controlled heights. This dimensional change allows contact area to be increased through vertical extension rather than lateral etching, avoiding the complexity of deep lateral etch techniques while achieving sufficient contact area with simpler vertical growth processes.
2Reliability
If contact metal is used to reduce external resistance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by carefully controlling the resistivity of the contact metal layer and optimizing its thickness parameter. By adjusting these parameters within specific ranges, the external resistance is reduced to acceptable levels for device performance without requiring overly complex multi-layer metal structures or additional processing steps.
Solution Approach 2:
The patent uses composite materials by combining the contact metal with the epitaxial semiconductor region to form an integrated contact structure. This composite approach allows the beneficial electrical properties of the metal to reduce resistance while the semiconductor portion maintains structural integration, achieving performance improvement without adding separate complex contact formation processes.
3Area of stationary object
If epitaxial nubs are formed to increase contact area, then external resistance is reduced, but process control requirements increase
Solution Approach 1:
The patent applies preliminary action by establishing the epitaxial nubs with their final desired dimensions before subsequent processing steps. The epitaxial growth process is controlled to achieve the target nub height and lateral dimensions in advance, allowing process control to be exercised when the structure is most controllable, rather than attempting to modify dimensions later through more difficult processes.
Solution Approach 2:
The patent applies parameter changes by controlling key epitaxial growth parameters such as temperature, pressure, gas flow rates, and precursor ratios to achieve precise control over nub dimensions. By optimizing these parameters within specific ranges, the contact area is maximized while maintaining acceptable process control and repeatability across manufacturing batches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reduced external resistance and improved process control, enhancing device drive and mobility while maintaining manufacturing efficiency and cost-effectiveness.
Implementation Method 1
stress-inducing contact metals to improve device performance
Implementation Method 2
epitaxial nubs
Data Source
AI summary
Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a semiconductor material; and a source/drain region at a side face of the channel region, wherein the source/drain region includes a semiconductor portion and a contact metal, and the semiconductor portion is between the contact metal and the semiconductor material.