Source/Drain Metal Contact Bottom-Up Growth Without Glue Layers
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Solution Overview
Problem
Current methods for forming device-level metal contacts in semiconductor fabrication, such as FinFET devices, face challenges in minimizing contact resistance and avoiding bottlenecks and voids, particularly when forming metal contacts over epitaxial source/drain features, as they often require glue layers with higher resistivity and are prone to defects like bottle necks and voids.
Innovation Solution
A unique fabrication process is employed where a silicide layer is formed over the epitaxial source/drain feature, followed by a seed metal layer, and a contact metal layer is selectively grown using a bottom-up approach directly on the silicide layer without a glue layer, ensuring minimal contact resistance and avoiding bottlenecks and voids by using higher conductive metals and optimizing deposition conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a glue layer is used to form metal contacts over epitaxial source/drain features, then adhesion is improved, but contact resistance increases due to higher resistivity of the glue layer
Solution Approach 1:
The patent removes the glue layer from the contact structure, eliminating the high-resistivity intermediate layer that caused increased contact resistance. The metal contact is formed directly on the epitaxial source/drain feature, extracting the problematic adhesive layer while maintaining structural integrity through direct metal-to-semiconductor contact.
Solution Approach 2:
The patent employs a composite contact structure consisting of multiple metal layers (e.g., tungsten, cobalt, nickel) with different properties. This composite approach provides both mechanical strength for adhesion and low electrical resistance, replacing the single-layer glue structure with a multi-layer metal system that optimizes both adhesion and conductivity.
2Ease of manufacture
If conventional metal contact formation methods are used, then manufacturing simplicity is maintained, but defects such as bottlenecks and voids occur
Solution Approach 1:
The patent performs preliminary surface preparation and cleaning of the epitaxial source/drain feature before metal deposition. This preliminary action ensures a clean, defect-free surface that prevents bottleneck formation and voids during subsequent metal contact formation, addressing potential defects before they occur.
Solution Approach 2:
The patent replaces conventional mechanical deposition methods with advanced deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). These methods provide better conformal coverage and eliminate bottlenecks and voids by ensuring uniform metal layer formation without mechanical disruption.
3Area of stationary object
If feature sizes are decreased to increase functional density, then chip area efficiency is improved, but contact formation becomes more challenging
Solution Approach 1:
The patent changes the physical and chemical parameters of the contact formation process, including deposition temperature, pressure, and material composition. These parameter adjustments enable successful contact formation at smaller feature sizes by controlling adhesion and diffusion processes at reduced dimensions, maintaining reliability despite increased complexity.
Solution Approach 2:
The patent transitions from planar contact formation to three-dimensional contact structures, utilizing vertical stacking and multi-layer approaches. This dimensional change allows contacts to be formed in the vertical dimension rather than solely in the lateral plane, enabling higher functional density without proportionally increasing contact formation complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, minimizes bottlenecks and voids, and enhances the overall performance of the semiconductor device by allowing for more efficient metal contact formation without the need for high-resistivity glue layers, thereby improving chip area efficiency and carrier mobility.
Implementation Method 1
forming a silicide layer over the epitaxial source/drain feature
Implementation Method 2
a contact metal layer is selectively grown using a bottom-up approach directly on the silicide layer
Data Source
AI summary
A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.