Source/Drain Contact Height Below Gate Stack
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Solution Overview
Problem
The increasing number of gate vias in semiconductor devices poses a challenge as they may accidentally connect with source/drain regions due to process variations, limiting the landing areas for gate vias and compromising IC performance and manufacturing efficiency.
Innovation Solution
The introduction of a contact protection layer over source/drain contacts allows gate vias to land anywhere, including areas that overlap active regions, preventing accidental shorts and enabling more flexible design and process optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate vias are restricted to landing areas away from active regions, then accidental connections between gate vias and source/drain regions are prevented, but the number of available landing areas is insufficient for FETs with many gate vias
Solution Approach 1:
The patent introduces a vertical dimension solution by forming source/drain contacts at a lower elevation than the gate stack top surface. This height difference creates a protective topography where gate vias can land on gate structures without risking accidental connections to source/drain regions, effectively adding a vertical separation dimension to the traditionally planar layout problem.
Solution Approach 2:
The patent introduces dielectric material as an intermediary substance filling the space between gate vias and source/drain contacts. This dielectric layer acts as a protective mediator that physically isolates the conductive gate vias from the conductive source/drain contacts, preventing accidental electrical connections while allowing close spatial proximity.
2Ease of manufacture
If source/drain contacts are formed at the same level as gate structures, then manufacturing is simpler, but gate vias may accidentally connect with source/drain regions due to process variations
Solution Approach 1:
The patent implements beforehand cushioning by creating a protective topographic structure where source/drain contacts are formed at a lower elevation than the gate stack. This pre-established height difference serves as a built-in safety margin that compensates for potential process variations and misalignments during subsequent via formation, preventing accidental connections even when manufacturing precision varies.
3Adaptability or versatility
If more landing areas are provided outside active regions, then gate vias can be placed more freely, but the substrate area increases reducing functional density
Solution Approach 1:
The patent resolves the area conflict by transitioning from a two-dimensional planar constraint to a three-dimensional solution. By forming source/drain contacts below the gate stack level, the invention enables gate vias to be placed directly over active regions without increasing substrate footprint, thus maintaining high functional density while achieving via placement flexibility.
Data Source
AI summary
A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.