Source/Drain Contact Height Structure for Low-Capacitance Semiconductors
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Solution Overview
Problem
As semiconductor devices are scaled down to achieve higher integration density, reducing capacitance and ensuring electrical stability between contacts becomes increasingly important, while maintaining competitiveness and product quality, existing technologies face challenges in achieving reliable performance.
Innovation Solution
The semiconductor device design includes specific source/drain contact structures with barrier and filling films, and gate structures that optimize contact heights and configurations to enhance electrical stability and reduce parasitic capacitance, allowing for improved performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to achieve higher integration density, then integration density is improved, but electrical stability and capacitance control deteriorate
Solution Approach 1:
The patent applies local quality by creating different height levels for source/drain contacts relative to the gate structure. Specifically, the source/drain contacts are formed with varying heights where some portions are lower than the gate structure top surface while other portions are higher, allowing optimized electrical characteristics at different locations within the same device structure.
Solution Approach 2:
The patent introduces vertical dimensionality variation by forming source/drain contacts with multiple height levels relative to the gate structure. This multi-level contact structure adds a vertical dimension to the contact design, enabling better control over electrical stability and capacitance while maintaining high integration density.
2Reliability
If source/drain contact structures are optimized to reduce parasitic capacitance, then electrical stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the source/drain contact structure into multiple height levels, with first source/drain contacts having different heights than second source/drain contacts relative to the gate structure. This segmentation allows each contact portion to be optimized independently for electrical performance while managing parasitic capacitance.
Solution Approach 2:
The patent changes the height parameter of source/drain contacts to optimize electrical characteristics. By varying the height of different contact portions relative to the gate structure, the patent achieves better control over parasitic capacitance and electrical stability without requiring fundamentally new contact materials or structures.
Data Source
AI summary
A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.