Source/Drain Contact Structure With Oxide-Removed Barrier Interface

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Solution Overview

Problem

The increasing complexity of semiconductor manufacturing processes due to the scaling down of semiconductor devices, such as MOSFETs and finFETs, leads to challenges in minimizing contact resistance between contact structures and source/drain regions, which degrades the electrical conductivity and performance of these devices.

Innovation Solution

A method involving the formation of contact structures with specific diffusion barrier layers and conductive layers, including an oxide removal process to reduce the oxygen concentration at the interface between these layers, thereby minimizing contact resistance and enhancing electrical conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If scaling down semiconductor device dimensions to increase storage capacity and processing speed, then device performance and capacity are improved, but manufacturing process complexity increases and contact resistance increases

Engineering Contradiction:
Improvestorage capacity and processing speedVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The contact structure is segmented into multiple functional layers: a first diffusion barrier layer (e.g., TiN) deposited directly on the source/drain region, and a second diffusion barrier layer (e.g., Ru) deposited on the first diffusion barrier layer. This segmentation allows each layer to perform its specific function optimally, preventing oxygen diffusion while maintaining electrical conductivity, thereby resolving the contradiction between device scaling and contact resistance management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first diffusion barrier layer acts as an intermediary between the source/drain region and the second diffusion barrier layer. It prevents oxygen atoms from the interlayer dielectric from diffusing into the contact structure, while also serving as a nucleation layer for the second diffusion barrier layer. This intermediary layer resolves the contradiction by blocking harmful oxygen diffusion paths that become more significant at scaled dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If scaling down semiconductor device dimensions, then storage capacity and processing speed are improved, but contact resistance between contact structures and source/drain regions increases

Engineering Contradiction:
Improveprocessing speedVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure employs local quality by using different materials with specific properties at different locations: the first diffusion barrier layer (TiN) has high oxygen diffusion barrier properties and is placed directly at the oxygen exposure interface, while the second diffusion barrier layer (Ru) has excellent electrical conductivity and is placed on top. This localized material optimization reduces contact resistance by ensuring each layer performs its specific function optimally at the scaled dimensions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The contact structure uses a composite of two different diffusion barrier materials (TiN and Ru) with complementary properties. TiN provides superior oxygen diffusion blocking, while Ru provides excellent electrical conductivity. The composite structure combines these advantages, reducing contact resistance by preventing oxygen-induced degradation while maintaining low electrical resistance, which is critical for scaled devices.

Inventive Principle:
Principle #40Composite materials

3Reliability

If using diffusion barrier layers to prevent oxygen diffusion, then contact resistance is reduced, but device structure complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidcontact structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first diffusion barrier layer is deposited in advance, directly on the source/drain region, to establish an oxygen-blocking foundation before the second diffusion barrier layer is added. This preliminary action prevents oxygen diffusion paths from forming, and the subsequent second layer is deposited on this prepared surface, ensuring good adhesion and additional oxygen blocking. This sequential preliminary action reduces contact resistance while managing structural complexity through organized layer deposition.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed method effectively reduces contact resistance and improves the electrical performance of semiconductor devices by maintaining low oxygen concentrations at the interface of diffusion barrier layers, ensuring adequate conductivity and device integrity.

Implementation Method 1

performing a plasma etch process on the first conductive layer

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

depositing a first conductive layer in the contact opening using a first deposition process

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 3

depositing a second conductive layer on the first conductive layer using a second deposition process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20250234602A1Contact Structures in Semiconductor Devices
Publication Date: 2025.07.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250234602A1 patent drawing
  • US20250234602A1 patent drawing
  • US20250234602A1 patent drawing

AI summary

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a nanostructured layer on a substrate, forming a gate structure surrounding the nanostructured layer, forming a S/D region adjacent to the nanostructured layer, forming a contact opening on the S/D region, depositing a first conductive layer in the contact opening using a first deposition process, performing a plasma etch process on the first conductive layer, depositing a second conductive layer on the first conductive layer using a second deposition process different from the first deposition process, and depositing a metal layer on the second conductive layer.