Source/Drain Contact Landing With Raised Epitaxy for Low Resistance
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Solution Overview
Problem
Existing source/drain contacts for multi-gate devices, such as FinFETs and MBC transistors, face challenges in forming uniform and low-resistant connections due to the complexity of epitaxial layers with varying dopant concentrations and germanium content, leading to increased resistance and manufacturing complications.
Innovation Solution
The formation of p-type and n-type source/drain features with different raise heights, utilizing multiple epitaxial layers with specific dopant and germanium contents, ensures reliable and low-resistance contact formation by adjusting the height of these features to minimize loss and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple epitaxial layers with varying dopant concentrations and germanium content are used, then lattice mismatch is reduced and contact resistance is lowered, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The source/drain contact structure is segmented into multiple epitaxial layers with different dopant concentrations and germanium contents. Each layer serves a specific function: the first epitaxial layer has lower dopant concentration to reduce lattice mismatch, while the second epitaxial layer has higher dopant concentration to reduce contact resistance. This segmentation allows optimization of each layer's properties independently.
Solution Approach 2:
Different regions of the epitaxial structure are assigned different local properties. The first epitaxial layer near the semiconductor fin has lower dopant concentration and germanium content to match the lattice structure, while the second epitaxial layer at the contact interface has higher dopant concentration to provide low resistance. This local quality variation optimizes both lattice matching and electrical contact properties.
2Ease of manufacture
If source/drain contacts are formed with uniform structure, then manufacturing process is simplified, but resistance reduction and performance enhancement are limited
Solution Approach 1:
The epitaxial growth process is made dynamic by varying parameters during different growth stages. The first epitaxial layer is grown with specific dopant concentration and germanium content, then the second epitaxial layer is grown with different parameters. This dynamic adjustment of growth conditions allows optimization of both manufacturing feasibility and electrical performance.
Solution Approach 2:
Key parameters such as dopant concentration, germanium content, and layer thickness are changed between different epitaxial layers. The first layer uses lower dopant concentration (e.g., 1E19 to 1E20 atoms/cm³) and lower germanium content, while the second layer uses higher dopant concentration (e.g., 1E20 to 1E21 atoms/cm³) and higher germanium content. These parameter changes enable simultaneous achievement of low lattice mismatch and low contact resistance.
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but parasitic resistance reduction becomes more challenging
Solution Approach 1:
The contact structure uses a nested multi-layer epitaxial configuration where the first epitaxial layer is positioned beneath the second epitaxial layer. This nested structure allows each layer to contribute differently to resistance reduction: the first layer provides lattice matching while the second layer provides heavy doping for low contact resistance, enabling effective parasitic resistance management in scaled devices.
Solution Approach 2:
The source/drain contact structure employs composite epitaxial materials with varying compositions. The first epitaxial layer has a composition optimized for lattice matching (lower Ge content), while the second epitaxial layer has a composition optimized for electrical conductivity (higher Ge content and dopant concentration). This composite material approach enables simultaneous optimization of structural integrity and electrical performance in miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of stable and low-resistance source/drain contacts, improving device performance and manufacturing efficiency by reducing parasitic resistance and enhancing carrier mobility.
Implementation Method 1
an epitaxial source/drain feature may include multiple epitaxial layers. Some of the multiple epitaxial layers are formed to reduce lattice mismatch and some of the multiple epitaxial layers are heavily doped
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a first p-type epitaxial feature disposed over a first fin, a second p-type epitaxial feature disposed and spanning over a second fin and a third fin, an interlayer dielectric (ILD) layer over the first p-type epitaxial feature and the second p-type epitaxial feature, a first contact extending through the ILD layer to electrically couple to the first p-type epitaxial feature, and a second contact extending through the ILD layer to electrically coupled to the second p-type epitaxial feature. A bottom surface of the first contact is lower than a bottom surface of the second contact.