Semiconductor Source/Drain Contact Layout for Stress-Preserved CMOS Scaling
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and performance enhancement, particularly in managing short channel effects and optimizing channel region carrier mobility, especially for NFET and PFET regions.
Innovation Solution
The semiconductor device incorporates a substrate with NFET and PFET regions, featuring epitaxial patterns with n-type and p-type impurities respectively, and source/drain contacts with specific geometries and materials to apply stress, improving carrier mobility and reducing parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling technology is used to increase device density, then device density increases, but short channel effects worsen and carrier mobility decreases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional channel structures including suspended channels, bridge channels, and nanowire channels. This dimensional change enables better gate control over the channel region, effectively suppressing short channel effects while maintaining scaled dimensions for high device density.
Solution Approach 2:
The channel region is segmented into multiple independent three-dimensional channel structures (suspended channels, bridge channels, nanowires) that are spatially separated. This segmentation allows each channel to be independently controlled by the gate, improving overall device performance and reducing相互 interference between adjacent channels.
2Ease of manufacture
If conventional source/drain contacts are used, then manufacturing is simplified, but contact resistance is high and carrier mobility is reduced
Solution Approach 1:
The patent changes the geometric parameters of source/drain contacts by forming recesses in the epitaxial patterns and positioning contacts within these recesses. This parameter change reduces the contact area with the channel region, lowering parasitic capacitance and contact resistance while maintaining manufacturability through standard etching and deposition processes.
Solution Approach 2:
The patent applies stress to the channel region through epitaxial patterns with different lattice constants, creating mechanical stress fields analogous to pneumatic/hydraulic systems. This stress modulation enhances carrier mobility in the channel without requiring direct contact modification, thereby maintaining ease of manufacture while improving electrical performance.
3Reliability
If epitaxial patterns with impurities are introduced to improve carrier mobility through stress, then carrier mobility increases, but parasitic capacitance increases
Solution Approach 1:
The epitaxial patterns are segmented into discrete regions with specific impurity concentrations positioned away from the channel contact interface. This segmentation allows stress to be applied to the channel for improved mobility while minimizing the capacitive coupling between highly doped regions and the channel, thereby reducing parasitic capacitance.
Solution Approach 2:
The patent applies different impurity concentrations and stress conditions to different local regions of the epitaxial patterns. High stress regions are positioned to maximize channel mobility enhancement, while regions near contacts are optimized to minimize parasitic capacitance, achieving local quality optimization throughout the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances performance by maintaining stress in PFET regions, reducing contact resistance, and minimizing parasitic capacitance, leading to improved semiconductor device performance.
Implementation Method 1
improving carrier mobility and reducing parasitic capacitance and contact resistance
Data Source
Figure 1~2
Figure 3A
Figure 3B
AI summary
A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.