Multi-Layer Source/Drain Contact Structure for Scaled 3D Transistors
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling density and mitigating short channel effects, particularly in multi-gate transistors, where efficient current control and reliability are compromised due to limitations in gate length and channel disruption.
Innovation Solution
The semiconductor device incorporates a multi-layer source/drain contact structure with tungsten layers having different crystal orientations, formed through physical vapor deposition processes, which includes grain boundaries to enhance contact efficiency and reliability in a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-gate transistor with 3D channel is used to increase device density and improve current control, then scaling is facilitated and short channel effect is mitigated, but the gate length cannot be increased to further improve current control capabilities
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional 3D channel structures (such as nanosheet and nanowire configurations). This dimensional change enables the gate to control current through multiple interfaces (top, bottom, and sidewalls), effectively increasing the controlled channel area without proportionally increasing the gate length, thus improving current control capability while maintaining scaled dimensions.
2Reliability
If the gate length is increased to improve current control, then current control capability is enhanced, but the device area increases and scaling density is reduced
Solution Approach 1:
By employing 3D channel structures such as nanosheets stacked vertically or nanowires extending in multiple directions, the patent increases the effective channel area controlled by the gate without increasing the lateral device footprint. The gate controls current through multiple interfaces (top, bottom, and sidewalls), achieving enhanced current control within a compact area that supports high device density.
Solution Approach 2:
The patent implements nested channel structures where multiple nanosheets or nanowires are stacked or arranged within a compact vertical or three-dimensional space. This nesting approach allows the gate to control multiple channel paths simultaneously, effectively increasing the total controlled channel area without proportionally increasing the lateral device area, thus maintaining scaling density while improving current control.
3Reliability
If conventional single-layer source/drain contact is used, then manufacturing is simpler, but contact resistance is higher and reliability is reduced
Solution Approach 1:
The patent divides the source/drain contact into multiple sequential layers (first layer, second layer, third layer) with different crystal orientations. Each layer serves a specific function in reducing contact resistance, and the segmented structure allows optimization of each layer's properties independently, achieving improved contact reliability while managing manufacturing complexity through systematic multi-layer formation.
Solution Approach 2:
The patent assigns different crystal orientations to different layers of the source/drain contact structure. Specifically, the first layer has a first crystal orientation, the second layer has a second crystal orientation different from the first, and the third layer has a third crystal orientation different from the second. This local differentiation of crystal orientation optimizes electrical properties at each interface, reducing overall contact resistance and improving contact reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and reduces resistance of the source/drain contact, effectively addressing scaling density and short channel effects while maintaining efficient current control.
Implementation Method 1
formed through physical vapor deposition processes
Data Source
AI summary
A semiconductor device may include a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least a first side of the gate electrode on the active pattern, and a source/drain contact connected to the source/drain region on the first side of the gate electrode. The source/drain contact may include first, second, and third layers which are sequentially stacked, the first to third layers including the same metal, with each layer having a respective crystal orientation. The source/drain contact may include a first grain boundary at an interface between the first layer and the second layer, and a second grain boundary at an interface between the second layer and the third layer.