3D Source/Drain Contact Trench Layout for Lower Contact Resistance
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Solution Overview
Problem
The increasing complexity and challenges in semiconductor manufacturing processes, particularly in scaling down semiconductor IC dimensions, have led to difficulties in achieving low-cost, high-performance, and low-power integrated circuits, with existing multi-gate devices facing issues in gate control and short-channel effects.
Innovation Solution
The development of a method for fabricating multi-gate devices, such as FinFETs and GAA transistors, with optimized source/drain contacts that provide a direct, shortest conductive path to channel regions, minimizing lateral distance and reducing current cladding, using techniques like epitaxial growth, patterning, and spacer formation to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact structures are used in multi-gate devices, then manufacturing is simpler, but resistance is higher and gate control is reduced
Solution Approach 1:
The patent transitions from planar 2D contact structures to three-dimensional contact configurations that wrap around and directly touch the channel region from multiple directions. This dimensional change enables shorter conductive paths and better gate control by positioning contacts in 3D space around the channel rather than merely at the surface level.
Solution Approach 2:
The contact regions are formed and positioned before final device assembly, with epitaxial growth and spacer formation performed in advance to create pre-positioned contact structures. This preliminary action ensures optimal contact geometry is established early in the fabrication process, enabling subsequent steps to focus on device completion rather than contact formation.
2Reliability
If source/drain contacts are positioned farther from channel regions, then manufacturing is easier, but lateral distance increases causing higher resistance
Solution Approach 1:
Spacer structures serve as intermediary elements that precisely define and position the contact regions relative to the channel. These spacers act as temporary mediators during fabrication, enabling accurate spatial relationships to be established between contacts and channels through controlled deposition and etching processes.
Solution Approach 2:
The patent employs epitaxial growth to precisely control the dimensions, composition, and doping levels of contact regions. By adjusting growth parameters such as temperature, pressure, and precursor flow rates, the contact structure geometry and electrical properties are optimized to achieve low resistance while maintaining precise positioning.
3Productivity
If multi-gate devices are scaled down, then device density increases, but gate control and electrostatic control deteriorate
Solution Approach 1:
The patent utilizes three-dimensional contact structures that extend vertically and wrap around the channel region, providing gate control from multiple spatial directions. This 3D configuration maintains effective gate control even as device dimensions are reduced, allowing continued scaling while preserving electrostatic control through enhanced gate-channel coupling in three-dimensional space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing resistance and enhancing gate control, mitigating short-channel effects, and enabling further scaling while maintaining electrostatic control, thus advancing semiconductor manufacturing technology.
Implementation Method 1
etching a portion of the source/drain feature to form a trench
Implementation Method 2
forming a conductive contact to the source/drain feature in the trench
Data Source
AI summary
Provided are semiconductor structures and methods for fabricating semiconductor structures. A method includes forming a stack of semiconductor nanosheets over a substrate; forming a source/drain feature adjacent to the stack; etching a portion of the source/drain feature to form a trench, wherein the trench extends to a horizontal plane at or below a lowest surface of a lowest semiconductor nanosheet in the stack; and forming a conductive contact to the source/drain feature in the trench.