Multi-Side Source/Drain Contacts for Lower Resistance in Scaled FETs
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Solution Overview
Problem
Conventional contact formation schemes in highly scaled multi-gate FETs result in increased transistor contact resistance, limiting device performance.
Innovation Solution
The development of novel source/drain contacts with reduced contact resistance for multi-gate transistors, involving the formation of deep contact holes and the use of semiconductor-metal alloys and metallic materials to enhance contact area and reduce energy barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation schemes are used in highly scaled multi-gate FETs, then the fabrication process remains simple, but the transistor contact resistance increases significantly, limiting device performance
Solution Approach 1:
The contact formation process is segmented into multiple distinct steps: forming contact holes through the interlayer dielectric, depositing a first contact material (e.g., titanium or cobalt), depositing a second contact material (e.g., tungsten or copper), and performing selective removal operations. This segmentation allows each material layer to be optimized for its specific function, thereby reducing overall contact resistance while maintaining process manageability
Solution Approach 2:
The contact structure transitions from a conventional planar contact to a three-dimensional multi-layer contact structure that extends vertically through the interlayer dielectric. This dimensional change enables increased contact area with the source/drain regions without increasing the lateral footprint, thereby reducing contact resistance in highly scaled devices
2Productivity
If the transistor device structure is scaled down to multi-gate FETs, then the drive current and control of short-channel effects are improved, but the contact resistance impact on device performance increases beyond 50%
Solution Approach 1:
The contact structure employs composite materials consisting of multiple metal layers with different properties. The first contact material (e.g., titanium or cobalt) provides good adhesion to the semiconductor and low contact resistance, while the second contact material (e.g., tungsten or copper) provides low resistivity and good electrical conductivity. This composite structure reduces overall contact resistance impact, ensuring that multi-gate FETs maintain high drive current capability
Solution Approach 2:
The contact holes are formed and the first contact material is deposited before the final interlayer dielectric structure is complete. This preliminary action allows the contact materials to be in direct contact with the source/drain regions during critical processing steps, ensuring optimal contact formation and minimizing contact resistance before subsequent processing steps
Data Source
AI summary
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.