Source/Drain Diffusion Barrier Layers for Threshold Voltage Uniformity

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Solution Overview

Problem

The diffusion of high-concentration dopants from epitaxial source/drain layers into the substrate in transistors leads to increased resistance and non-uniform threshold voltages, affecting transistor performance and switching speed.

Innovation Solution

Incorporation of diffusion barrier layers between epitaxial source/drain layers and the semiconductor substrate to mitigate and block the diffusion of dopants, maintaining high dopant concentration and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-concentration dopants are used in epitaxial source/drain layers to reduce resistance, then electrical conductivity improves, but dopant diffusion into the substrate increases causing non-uniform threshold voltages

Engineering Contradiction:
Improvetransistor performanceVSAvoiddopant concentration uniformity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

A diffusion barrier layer is introduced as an intermediary between the epitaxial source/drain layers and the semiconductor substrate. This barrier layer selectively blocks dopant diffusion into the substrate while permitting beneficial dopant retention in the source/drain regions, thereby resolving the contradiction between achieving low resistance and maintaining compositional stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure is segmented into distinct functional layers: the epitaxial source/drain layers containing high-concentration dopants for low resistance, and a separate diffusion barrier layer to prevent unwanted dopant migration. This segmentation allows each layer to optimize its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

2Speed

If dopant concentration in source/drain layers is increased to improve switching speed, then RDS(on) decreases, but diffusion into substrate causes threshold voltage non-uniformity

Engineering Contradiction:
Improveswitching speedVSAvoidthreshold voltage uniformity
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The diffusion barrier layer serves as a mediator that enables high dopant concentration in source/drain regions for fast switching while preventing dopant contamination of the substrate that would cause threshold voltage variations, thus achieving both high speed and manufacturing precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Power

If epitaxial source/drain layers are used to reduce resistance, then current rating increases, but dopant diffusion into substrate occurs affecting transistor performance

Engineering Contradiction:
Improvecurrent ratingVSAvoidtransistor performance consistency
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The diffusion barrier layer acts as a protective intermediary that allows the epitaxial source/drain layers to maintain high dopant concentration for high current rating while preventing dopant diffusion into the substrate that would compromise transistor performance consistency across the device array.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach maintains low resistance and uniform threshold voltages across an array of transistors, enhancing switching speed and current rating.

Implementation Method 1

The diffusion of high-concentration dopants from epitaxial source/drain layers into the substrate in transistors leads to increased resistance and non-uniform threshold voltages

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20250366108A1Diffusion barrier layer for source and drain structures to increase transistor performance
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366108A1 patent drawing
  • US20250366108A1 patent drawing
  • US20250366108A1 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. The first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. The first pair of source/drain regions comprise a first dopant. The diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. A doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.