Source/Drain Structure With Diffusion Layer for Lower Channel Resistance
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce the channel resistance of field effect transistors (FETs) to enhance processing speed, which is hindered by the underlap between the gate terminal and the source/drain terminal.
Innovation Solution
The introduction of a diffusion enhancement layer, typically a silicon germanium layer, sandwiched between the channel region and the source/drain region, facilitates the diffusion of dopants from the source/drain region towards the channel region, thereby reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an underlap structure is used between gate terminal and source/drain terminal, then device complexity is reduced and manufacturing is simplified, but channel resistance increases leading to slower processing speed
Solution Approach 1:
A diffusion enhancement layer is introduced as an intermediary component between the source/drain region and the channel region. This layer mediates the dopant diffusion process, enabling effective dopant transfer from the source/drain region to the channel region despite the underlap structure, thereby reducing channel resistance without requiring gate overlap
Solution Approach 2:
The diffusion enhancement layer utilizes material composition parameters (such as silicon germanium with specific germanium concentrations) to enhance dopant diffusion. By changing the material parameters of this intermediate layer, dopant diffusion is significantly improved, allowing the underlap structure to achieve low channel resistance
2Productivity
If channel resistance is reduced to improve processing speed, then productivity increases, but device complexity increases due to additional diffusion enhancement layer
Solution Approach 1:
The diffusion enhancement layer is formed in advance during the epitaxial growth process, before final device assembly. This preliminary action of pre-forming the enhancement layer with appropriate material composition enables subsequent efficient dopant diffusion, achieving high processing speed without requiring complex post-processing steps
Solution Approach 2:
The diffusion enhancement layer employs composite material structure (such as silicon germanium alloy with graded composition) to achieve enhanced dopant diffusion. This composite approach allows the structure to provide both mechanical support and diffusion enhancement functions, improving processing speed while maintaining reasonable structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the channel resistance of transistors, leading to improved on-current and overall performance of FETs.
Implementation Method 1
facilitates the diffusion of dopants from the source/drain region towards the channel region
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.