Source/Drain Dopant Cluster Structure for Etch Damage Reduction
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Solution Overview
Problem
The continuous scaling down of semiconductor device dimensions and increasing demand for device performance lead to challenges such as gate-S/D short defects and etching damage during the sheet formation process of nanostructure transistors, resulting in device failure and yield loss.
Innovation Solution
The introduction of a dopant cluster in the source/drain structure, specifically a high-concentration dopant cluster extending along the (111) growth planes of the second epitaxial layer, which enhances etch resistance and reduces gate-S/D short defects, improving device performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuous scaling down of semiconductor device dimensions is pursued, then higher storage capacity and processing performance are achieved, but gate-S/D short defects and etching damage increase
Solution Approach 1:
The patent applies local quality by introducing a dopant cluster with high concentration (first concentration) specifically at the source/drain structure interface, while maintaining lower dopant concentration in other regions. This localized high-concentration dopant cluster enhances etch resistance precisely where needed to prevent gate-S/D short defects during scaling, without adversely affecting other device regions.
Solution Approach 2:
The patent utilizes parameter changes by varying the dopant concentration parameter spatially - implementing a first concentration in the dopant cluster region and a second (lower) concentration elsewhere. This concentration gradient modifies the material properties locally to enhance etch resistance and prevent defects during continuous dimension scaling.
2Productivity
If continuous scaling down of semiconductor device dimensions is pursued, then higher storage capacity is achieved, but etching damage during sheet formation process increases
Solution Approach 1:
The dopant cluster is strategically positioned at the source/drain structure interface where etching damage occurs during sheet formation. The high dopant concentration in this specific region creates enhanced etch resistance, protecting the structure from harmful etching effects while allowing continuous scaling for higher storage capacity.
Solution Approach 2:
The high-concentration dopant cluster is introduced beforehand during epitaxial growth to create a protective layer with enhanced etch resistance. This pre-established protective structure cushions against subsequent etching damage during the sheet formation process, enabling continuous scaling without excessive damage.
3Reliability
If dopant cluster with high concentration is introduced in source/drain structure, then etch resistance and device yield are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the dopant cluster formation with the epitaxial growth process itself, rather than using separate doping steps. By incorporating the high-concentration dopant cluster during the epitaxial growth of the source/drain structure, the manufacturing process integrates multiple functions into a single step, reducing overall process complexity while achieving enhanced etch resistance and device yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dopant cluster reduces etching damage to the source/drain structure, minimizes gate-S/D short defects, and enhances the overall performance and yield of semiconductor devices by increasing etch resistance and reducing contact resistance.
Implementation Method 1
The introduction of a dopant cluster in the source/drain structure, specifically a high-concentration dopant cluster extending along the (111) growth planes of the second epitaxial layer, which enhances etch resistance and reduces gate-S/D short defects
Implementation Method 2
enhances the overall performance and yield of semiconductor devices by increasing etch resistance and reducing contact resistance
Data Source
AI summary
The present disclosure describes a semiconductor device having a source/drain structure with a dopant cluster. The semiconductor device includes a channel structure on a substrate and a source/drain structure on the substrate and adjacent to the channel structure. The source/drain structure includes a first epitaxial layer on the substrate, a second epitaxial layer on the first epitaxial layer and sidewalls of the channel structure, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes a cluster of a dopant extending along a direction of the channel structure.


