Source/Drain SiGe Structure With Dopant Clusters for Low Contact Resistance

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Solution Overview

Problem

Existing semiconductor technologies face challenges in reducing transistor contact resistance, which limits transistor speed and performance due to the limited solid solubility of dopants in semiconductor materials, resulting in insufficient donors or acceptors in integrated circuits.

Innovation Solution

A fabrication method that incorporates clusters of dopants embedded in the source/drain regions of transistors using a doped epitaxial stack, comprising multiple layers of silicon germanium (SiGe) with varying dopant concentrations to reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If heavily doped source/drain terminals are used to reduce contact resistance, then transistor speed increases, but the solid solubility limit of dopants restricts further improvement

Engineering Contradiction:
Improvecontact resistanceVSAvoiddopant concentration
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the physical state and distribution parameters of dopants by forming nanoscale clusters instead of uniform doping. This transforms the dopant distribution from a homogeneous state to a clustered state with local high concentration regions, effectively bypassing the solid solubility limit while achieving lower contact resistance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a composite structure within the source/drain region by combining silicon germanium (SiGe) material with clustered dopant phases. This composite approach allows the system to achieve dopant concentrations exceeding the solid solubility limit of pure silicon, utilizing the different solubility characteristics of dopants in SiGe versus Si

Inventive Principle:
Principle #40Composite materials

2Productivity

If dopant concentration is increased to reduce contact resistance, then transistor performance improves, but dopant solid solubility limits the maximum achievable concentration

Engineering Contradiction:
Improvetransistor speedVSAvoiddopant concentration
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent transforms the dopant distribution parameter from uniform concentration to clustered distribution, creating local regions with very high dopant concentration that exceed the solid solubility limit. This parameter change enables achieving the necessary dopant quantity for low contact resistance without being constrained by the bulk solid solubility limit

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a new spatial dimension to dopant distribution by forming nanoscale clusters (0-10 nm scale) within the source/drain region. This clustered distribution in three-dimensional space allows the system to achieve high effective dopant concentration while maintaining a larger overall volume, effectively bypassing the solid solubility constraint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively lowers contact resistance, enhancing transistor performance by improving the distribution and concentration of dopants, thereby increasing speed and efficiency.

Implementation Method 1

precipitating the second dopant to form a cluster of the second dopant in the second epitaxial layer

Methodology Applied
Scientific EffectPrecipitation: Precipitation

Data Source

PatentUS20250287630A1Source/drain structure for semiconductor device
Publication Date: 2025.09.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250287630A1 patent drawing
  • US20250287630A1 patent drawing
  • US20250287630A1 patent drawing

AI summary

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.