Multi-Layered Source/Drain Doping for Short-Channel FinFETs
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Solution Overview
Problem
As transistor sizes decrease, the short-channel effect becomes a significant issue due to the channel length approaching the depletion-layer widths, affecting transistor performance, and there is a need for structures and processing methods that can accommodate small feature sizes in advanced semiconductor technologies.
Innovation Solution
The formation of FinFET devices with multi-layered source/drain regions having different dopant concentrations, where a non-conformal first semiconductor layer with a lower dopant concentration is etched to form a thicker portion proximate the top surface and a thinner portion between the top and bottom, followed by a second semiconductor layer with a higher dopant concentration, which helps in reducing current leakage and creating a depletion region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor channel length is reduced to increase integration density, then more components can be integrated into a given area, but short-channel effect appears which adversely affects transistor performance
Solution Approach 1:
The patent applies local quality by creating multi-layered source/drain regions with different dopant concentrations at different locations within the same transistor structure. Specifically, the source and drain regions have higher dopant concentrations near the channel to control depletion width and threshold voltage, while having lower concentrations in other areas to reduce leakage. This spatial variation in dopant concentration allows the transistor to maintain high integration density with reduced channel length while compensating for short-channel effects through localized doping optimization.
Solution Approach 2:
The patent utilizes parameter changes by varying the dopant concentration parameter throughout the source and drain regions. The multi-layered structure creates gradients in dopant concentration, with higher concentrations near the channel interface and lower concentrations extending outward. This parameter variation enables control over the depletion region width and electric field distribution, allowing the device to achieve both high integration density and acceptable transistor performance despite reduced channel dimensions.
2Productivity
If channel length is reduced to increase integration density, then more components fit in given area, but depletion-layer widths become comparable to channel length causing short-channel effects
Solution Approach 1:
The patent addresses the harmful short-channel effect by implementing local quality through spatially varying dopant concentrations in the source and drain regions. By concentrating higher dopant levels near the channel ends, the depletion region width is locally controlled to prevent it from extending too far into the channel, thereby mitigating short-channel effects while maintaining the reduced channel length necessary for high integration density.
Solution Approach 2:
The patent applies preliminary anti-action by pre-configuring the source and drain regions with optimized multi-layered dopant profiles before the transistor operates. This preliminary doping structure creates appropriate electric field distributions and depletion region boundaries that counteract the adverse effects of short channel length, preventing short-channel effects from manifesting during device operation while allowing high integration density to be achieved.
Data Source
AI summary
A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.