Source/Drain Epitaxial Layer Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing integration and reduction in size of semiconductor devices lead to challenges in achieving high power efficiency, particularly due to increased parasitic capacitance from stacked channel layers, which affects performance and power consumption.
Innovation Solution
A semiconductor device design featuring active regions with intersecting gate structures and source/drain regions having epitaxial layers of different thicknesses and depths, optimized to improve power efficiency by configuring the source/drain regions according to transistor characteristics, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased and device size is reduced, then high performance and high speed are achieved, but power efficiency deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent applies local quality by forming source/drain regions with different epitaxial layer thicknesses in different locations. Specifically, a first epitaxial layer is formed with a first thickness in a first source/drain region, and a second epitaxial layer is formed with a second thickness (different from the first) in a second source/drain region. This localized variation in layer thickness allows optimization of parasitic capacitance in specific areas while maintaining overall device performance.
Solution Approach 2:
The patent changes physical parameters by varying the thickness of epitaxial layers in source/drain regions. The first epitaxial layer has a first thickness in the first source/drain region and a second thickness (less than the first) in the second source/drain region. This parameter variation enables control over parasitic capacitance characteristics, thereby improving power efficiency while maintaining high integration and performance.
2Productivity
If stacked channel layers are used to maintain performance in reduced size devices, then integration is improved, but parasitic capacitance increases reducing power efficiency
Solution Approach 1:
The patent applies local quality by forming source/drain regions with different epitaxial layer thicknesses in different locations. Specifically, a first epitaxial layer is formed with a first thickness in a first source/drain region, and a second epitaxial layer is formed with a second thickness (different from the first) in a second source/drain region. This localized variation in layer thickness allows optimization of parasitic capacitance in specific areas while maintaining overall device performance.
Solution Approach 2:
The patent changes physical parameters by varying the thickness of epitaxial layers in source/drain regions. The first epitaxial layer has a first thickness in the first source/drain region and a second thickness (less than the first) in the second source/drain region. This parameter variation enables control over parasitic capacitance characteristics, thereby improving power efficiency while maintaining high integration and performance.
Data Source
AI summary
A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.