Recessed Source/Drain Epitaxy With Diffusion Width Control
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Solution Overview
Problem
In semiconductor devices, the depth of epitaxial layers in recessed portions of the semiconductor substrate varies due to microloading effects during etching, leading to inconsistent stress applied to channel regions and increased junction leakage due to crystal defects.
Innovation Solution
The semiconductor device incorporates epitaxial layers and diffusion layers in the source/drain regions, where the width of the epitaxial layers is controlled by adjusting the width of the diffusion layers, thereby controlling the depth of the recessed portions and reducing the layout-dependent variation in epitaxial layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the recessed area is reduced to decrease layout area, then the microloading effect increases causing greater variation in epitaxial layer depth, but larger layout area increases crystal defects and junction leakage
Solution Approach 1:
The patent changes the controlling parameter from recess area to diffusion layer width. By controlling the width of the diffusion layer formed in the silicon substrate, the epitaxial layer width is precisely controlled regardless of the recess dimensions. This parameter substitution resolves the microloading effect issue because diffusion layer width can be controlled with high precision through ion implantation or in-diffusion processes, independent of the recess area variations.
2Stress or pressure
If the recess depth is increased to improve stress control, then the epitaxial layer depth increases improving stress application, but the etching process becomes more sensitive to microloading effects
Solution Approach 1:
The patent introduces the diffusion layer as an intermediary element between the silicon substrate and the epitaxial layer. The diffusion layer serves as a width-defining mask that controls the epitaxial layer formation area. This intermediary allows precise control of epitaxial layer width through the diffusion layer width, while the recess depth can be independently optimized for stress application without being constrained by microloading effects on width control.
3Stress or pressure
If the epitaxial layer width is increased to improve stress effect, then more stress is applied to channel region, but the layout area increases leading to more crystal defects
Solution Approach 1:
The patent changes the controlling parameter from recess area to diffusion layer width, enabling precise control of epitaxial layer width. This allows optimization of epitaxial layer width for adequate stress application while maintaining small layout area, thereby reducing crystal defects. The diffusion layer width serves as a precise control parameter that decouples stress effect optimization from layout area constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for uniform control of the epitaxial layer depth, reducing stress variation in channel regions and minimizing crystal defects, which in turn improves transistor characteristics and reduces junction leakage.
Implementation Method 1
an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode
Implementation Method 2
the source/drain regions being formed by implanting impurities
Implementation Method 3
a diffusion layer formed by diffusing impurities into the surface layer of the semiconductor substrate
Data Source
AI summary
A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.