Source/Drain Epitaxial Layer Layout Near Isolation Structures
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Solution Overview
Problem
In CMOS FETs, the challenge of preventing drain induced barrier lowering (DIBL) and latch-up becomes more significant with increasing down-scaling and speed requirements, particularly due to insufficient growth of source/drain epitaxial layers near isolation structures, leading to reduced driving current and asymmetric device characteristics.
Innovation Solution
A method is introduced to form source/drain epitaxial layers by etching recesses in active regions near isolation structures, ensuring sufficient growth by maintaining a crystalline semiconductor boundary, thereby enhancing the epitaxial volume and achieving symmetric profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If source/drain epitaxial layers are grown near isolation structures, then the driving current is improved, but the epitaxial growth becomes insufficient leading to asymmetric device characteristics
Solution Approach 1:
The source/drain region is divided into two distinct epitaxial layers: a first source/drain epitaxial layer grown near the isolation structure and a second source/drain epitaxial layer grown away from it. This segmentation allows each layer to be optimized independently, with the first layer providing sufficient growth volume near the isolation structure and the second layer ensuring proper epitaxial characteristics, thereby resolving the contradiction between achieving sufficient driving current and maintaining growth uniformity.
2Speed
If down-scaling of integrated circuits is increased, then the speed requirements are met, but latch-up and DIBL prevention become more difficult
Solution Approach 1:
Different regions of the source/drain structure are given different qualities through the dual-layer epitaxial approach. The first epitaxial layer near the isolation structure has optimized properties for preventing latch-up and DIBL, while the second layer maintains the epitaxial characteristics needed for high-speed operation. This local differentiation allows the device to simultaneously achieve high speed and reliability despite down-scaling challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher driving current and lower leakage current, while improving DIBL properties by ensuring uniform epitaxy growth and reducing latch-up issues.
Implementation Method 1
an epitaxial semiconductor layer is formed in the recess
Data Source
AI summary
In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.