Shaped Source/Drain Epitaxy for FinFET Yield and Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to create large epitaxial source/drain structures for Fin FETs that enhance device performance without adversely affecting yield, particularly in high-density integrated circuits like SRAM chips, while managing issues related to sheet resistance and contact resistivity.
Innovation Solution
A method involving high-temperature epitaxial growth and modified etch processes is employed to control the crystallographic facet growth of source/drain structures, promoting (100) orientation and reducing (110) and (111) orientations, resulting in SD epitaxial structures with flat sides and controlled dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large epitaxial source/drain volume is used to improve device performance, then device performance is improved, but yield is adversely affected in high-density integrated circuits
Solution Approach 1:
The patent applies local quality by creating different epitaxial growth conditions in different regions of the semiconductor structure. Specifically, it forms source/drain epitaxial structures with controlled crystallographic orientations ((100), (110), (111) facets) in specific locations, and uses selective masking to control where large-volume epitaxial growth occurs. This allows large epitaxial volume to be concentrated in regions where performance is critical while limiting it in regions where high density is prioritized, thus resolving the contradiction between device performance and yield.
2Reliability
If epitaxial growth process is used to create source/drain structures, then device performance is enhanced, but unwanted contacts and leakage increase
Solution Approach 1:
The patent employs asymmetry by controlling the epitaxial growth to create non-uniform crystallographic facet distributions. By selectively promoting certain orientations ((100), (110), or (111) facets) in specific areas through tailored growth conditions and masking, the structure achieves asymmetric properties that enhance performance in active regions while suppressing unwanted contacts and leakage in other regions. This directional control of crystal growth resolves the contradiction between performance enhancement and harmful side effects.
3Productivity
If fin pitch scaling is pursued to increase device density, then device density is improved, but sheet resistance and contact resistivity issues arise
Solution Approach 1:
The patent applies parameter changes by systematically varying epitaxial growth parameters (temperature, pressure, gas flow rates, precursor ratios) to control crystallographic facet formation and source/drain structure morphology. By adjusting these parameters, the process optimizes the balance between achieving sufficient epitaxial volume for low resistance and maintaining compact structures for high density. This dynamic parameter control resolves the contradiction between device density and electrical resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by minimizing unwanted contacts and leakage, ensuring high yield and reliability in high-density integrated circuits.
Implementation Method 1
A source/drain epitaxial structure is formed in the trench
Implementation Method 2
high-temperature epitaxial growth and modified etch processes is employed to control the crystallographic facet growth of source/drain structures, promoting (100) orientation and reducing (110) and (111) orientations
Data Source
AI summary
In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.


