Source/Drain Epitaxial Layer Layout for Device Matching

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Solution Overview

Problem

In the design of integrated circuits, there is a challenge in achieving consistent performance due to the complexities of smaller feature sizes and stringent design constraints, particularly in the matching behavior of devices, which affects the reliability and efficiency of semiconductor devices.

Innovation Solution

A method of fabricating semiconductor devices involves forming a substrate with a metal layer and dielectric layers, patterning these layers to create openings, and performing annealing processes in hydrogen-rich atmospheres to reduce defects and electrical characterization mismatches, thereby improving device matching and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If feature sizes are reduced to advance technology, then device density and integration are improved, but device matching behavior and performance consistency deteriorate

Engineering Contradiction:
Improvefeature sizeVSAvoiddevice matching behavior
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the annealing process conditions (temperature, atmosphere composition, duration) to optimize device matching behavior at reduced feature sizes. Specifically, annealing in hydrogen-rich atmospheres at controlled temperatures adjusts material properties to compensate for scaling effects, thereby maintaining performance consistency despite smaller dimensions

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes inert atmosphere (hydrogen-rich environment) during annealing processes to create a controlled chemical environment that prevents oxidation and enables precise control over material properties. This inert environment allows for consistent device matching behavior by eliminating variable chemical reactions that would otherwise worsen with reduced feature sizes

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Reliability

If annealing processes are performed in hydrogen-rich atmospheres, then device matching and performance consistency are improved, but process complexity increases

Engineering Contradiction:
Improvedevice matchingVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by using hydrogen-rich atmosphere annealing as a multi-functional process that simultaneously achieves multiple objectives: removing defects, adjusting threshold voltage, improving device matching, and controlling material properties. This consolidates several process steps into one, reducing overall process complexity despite the sophisticated annealing conditions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the consistency and reliability of semiconductor devices by reducing device-to-device electrical mismatches and improving performance metrics such as threshold voltage, leading to more consistent and efficient semiconductor device operation.

Implementation Method 1

performing annealing processes in hydrogen-rich atmospheres to reduce defects and electrical characterization mismatches

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS11996323B2Semiconductor device with source/drain epitaxial layer
Publication Date: 2024.05.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11996323B2 patent drawing
  • US11996323B2 patent drawing
  • US11996323B2 patent drawing

AI summary

A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.