Source-Drain Epitaxial Structure for Lower FET Channel Resistance

A gate spacer is introduced as an intermediary structure between the gate terminal and the source/drain terminal. The gate spacer is positioned to overlap with the source/drain terminal, creating a physical and electrical bridge that reduces channel resistance while allowing the gate-terminal underlap to maintain reduced transistor delay. This intermediary structure resolves the contradiction by providing a pathway for charge carriers without requiring direct gate-source/drain overlap.

The structure is segmented into distinct regions: the gate terminal, the gate spacer, and the source/drain terminal. The gate spacer is separated from both the gate terminal and the source/drain terminal by controlled gaps, allowing each component to perform its function independently. This segmentation enables the gate spacer to reduce channel resistance through overlap with the source/drain terminal while the gate-terminal underlap maintains reduced transistor delay, avoiding the need for direct gate-source/drain overlap.

The gate spacer's physical and electrical parameters are optimized to achieve effective dopant diffusion enhancement. By controlling the gate spacer's thickness, material composition, and positioning, the structure enhances dopant diffusion into the channel region without requiring additional diffusion enhancement layers. This parameter optimization resolves the contradiction by achieving low channel resistance through the gate spacer's inherent properties rather than adding complex multi-layer structures.