Source/Drain Fin Spacer Structure for Precise Semiconductor Etching
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Solution Overview
Problem
The increased complexity of spacer structures in semiconductor devices due to higher integration levels can lead to poor etching processes, resulting in undesired shapes and sizes of device elements.
Innovation Solution
A semiconductor device design and manufacturing method that includes specific configurations of fin spacers, etch stop patterns, and capping layers to facilitate precise etching, ensuring consistent formation of source/drain layers and gate structures, even at reduced spacings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacer structure is made complex with multiple layers to accommodate increased integration, then the degree of integration increases, but the thickness of the spacer structure increases causing poor etching performance
Solution Approach 1:
The spacer structure is divided into multiple discrete layers (first spacer layer, second spacer layer, third spacer layer) with different materials and functions. Each layer is formed separately through distinct deposition and etching processes, allowing independent optimization of each layer's thickness and material properties to maintain etching precision while achieving high integration.
Solution Approach 2:
Different material parameters are selected for different spacer layers to optimize etching performance. The first spacer layer uses a material with specific etch selectivity, the second layer uses a different material with different etch resistance properties, and the third layer uses yet another material. This variation in material parameters allows each layer to be etched with appropriate control, preventing the thickness issue from degrading etching quality.
2Device complexity
If the spacer structure thickness increases to support complex multi-layer architecture, then more layers can be integrated, but the etching process cannot be performed well resulting in undesired shapes and sizes
Solution Approach 1:
The complex spacer structure is segmented into three distinct layers, each with controlled thickness and specific material composition. The first spacer layer has a first thickness, the second spacer layer has a second thickness, and the third spacer layer has a third thickness. This segmentation allows the overall complex structure to be built while maintaining precise control over each individual layer's dimensions, ensuring desired element shapes and sizes are achieved.
Solution Approach 2:
Each spacer layer is assigned different local qualities through material selection and thickness control. The first spacer layer near the substrate has different material properties than the second spacer layer in the middle, which in turn has different properties than the third spacer layer at the top. This local differentiation allows each region of the complex structure to be optimized for its specific function while maintaining overall manufacturing precision.
Data Source
AI summary
A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.