Source/Drain Conductive Layer Structure for Self-Aligned Flash Contacts

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Solution Overview

Problem

Current semiconductor manufacturing processes for flash memory devices face challenges in reducing contact resistance and increasing integration level due to complex and costly methods for forming conductive structures, which affect the performance and efficiency of the semiconductor structure.

Innovation Solution

A method involving the direct formation of an initial conductive layer on the source/drain doped layer, eliminating the need for a dielectric layer etching process, thereby simplifying the manufacturing process, reducing costs, and enhancing contact area and integration level by forming self-aligned conductive plugs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a self-align contact process is used to fabricate a conductive structure of a source/drain region, then the flash memory size can be reduced, but the contact resistance remains high and performance needs improvement

Engineering Contradiction:
Improveflash memory sizeVSAvoidcontact resistance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The conductive layer is extended from a planar configuration to a three-dimensional structure that covers both the top surface and sidewalls of the source/drain doped layer. This dimensional transition increases the contact area without increasing the lateral footprint, thereby reducing contact resistance while maintaining compact flash memory size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive layer is formed to cover the sidewall and top surface of the source/drain doped layer before subsequent processing steps. This preliminary formation of an extended conductive structure ensures low contact resistance is achieved early in the fabrication process, improving overall device performance.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a complex manufacturing process is used to form conductive structures, then contact resistance can be reduced, but the manufacturing cost and process complexity increase

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of the conductive layer covering both the top surface and sidewalls of the source/drain doped layer is achieved through a single integrated process step rather than multiple separate steps. This merging of operations simplifies the manufacturing process while effectively reducing contact resistance through the extended conductive structure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive layer serves multiple functions simultaneously: it provides electrical connection to the top surface of the source/drain doped layer and extends along the sidewall to increase contact area. This multi-functionality reduces the need for additional specialized structures or processes, thereby simplifying manufacturing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If a conventional contact formation process is used, then the manufacturing process is simpler, but the contact area is limited and performance is suboptimal

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidcontact area
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The conductive layer is designed to extend along the sidewall of the source/drain doped layer in addition to covering the top surface. This three-dimensional configuration increases the contact area without adding complex manufacturing steps, achieving both enhanced performance and ease of manufacture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250015162A1Semiconductor device
Publication Date: 2025.01.09 SEMICON MFG INT (SHANGHAI) CORP
  • US20250015162A1 patent drawing
  • US20250015162A1 patent drawing
  • US20250015162A1 patent drawing

AI summary

A semiconductor structure includes a substrate; a gate structure located on the substrate extending along a first direction; a source/drain doped layer in the substrate located on two sides of the gate structure; and a conductive layer on the source/drain doped layer and covering a sidewall and a top surface of the source/drain doped layer.