Source/Drain Contact Layout for Reduced Gate Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices shrink in size, short channel effects prevent further scaling down of planar field effect transistors, and multi-gate devices introduce increased parasitic resistance and capacitance due to thin dielectric layers between conductive structures, leading to performance issues.
Innovation Solution
A method for forming source/drain contacts that do not extend below the bottommost level of the gate structure, reducing the depth of the source/drain contact to minimize parasitic capacitance between the source/drain contact and the adjacent gate structure, achieved through a series of etch processes and dielectric layer management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If over-etching is performed to form source/drain contact opening, then source/drain contact can be formed into the opening, but lateral overlap between source/drain contact and gate structure increases causing undesirable parasitic capacitance
Solution Approach 1:
The gate structure is formed first before the source/drain contact opening is etched. This preliminary action allows the etch process to be precisely controlled to stop at the gate bottom surface, preventing over-etching and lateral overlap that would cause parasitic capacitance. The sequence ensures proper alignment and depth control of the contact opening.
Solution Approach 2:
The etch process uses plasma (a state of matter involving ionized gas) to selectively remove dielectric material. By controlling the plasma etch parameters and using the gate structure as an etch stop, the process precisely defines the contact opening depth and lateral dimensions, preventing overlap with the gate while ensuring proper contact formation.
2Productivity
If dielectric layers are made thinner to improve device scaling, then device density increases, but parasitic capacitance between gate structure and source/drain contact increases
Solution Approach 1:
The invention extracts or removes the source/drain contact laterally from the region where it would overlap with the gate structure. By defining the contact opening to align with the gate bottom surface and preventing lateral extension, the harmful parasitic capacitance region is extracted from the device structure, allowing thin dielectric layers to be used without the penalty of increased parasitic capacitance.
Solution Approach 2:
The dielectric layer thickness is optimized locally in different regions. In the contact region, the dielectric is precisely controlled to be thin enough for scaling but the contact is laterally constrained to prevent overlap. The gate bottom surface serves as a local reference plane that defines the maximum lateral extent of the contact, creating optimal local electrical characteristics.
Data Source
AI summary
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.