Source/Drain Contact Interface With Oxidation-Induced Ge Enrichment
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Solution Overview
Problem
Integrated circuits face significant inefficiencies and energy losses due to parasitic effects, particularly at the interface between source/drain features and contacts, which increase resistance and lead to energy wastage, heat production, reduced operating frequency, and potential device failure, especially in FinFETs with silicon-germanium alloy semiconductors.
Innovation Solution
A method is introduced to form a germanium-rich layer at the top of source/drain features through controlled oxidation, reducing resistance at the interface with contacts without requiring additional epitaxial deposition or implantation processes, thereby selectively improving the interface for SiGe-containing devices without affecting Si-containing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional epitaxial deposition or implantation processes are used to form a germanium-rich layer, then contact resistance is reduced, but manufacturing complexity and fabrication cost increase
Solution Approach 1:
The oxidation process automatically segregates germanium to the surface of the source/drain feature through self-diffusion mechanisms, forming a germanium-rich layer without requiring additional epitaxial deposition or implantation processes. The material's inherent properties drive the segregation during the oxidation process itself.
Solution Approach 2:
The patent changes the chemical composition parameters of the source/drain feature surface by performing controlled oxidation, which induces germanium segregation to the interface region. This parameter change (oxidation state) automatically creates the desired germanium-rich layer without additional deposition steps.
2Reliability
If additional epitaxial deposition or implantation processes are used to form a germanium-rich layer, then contact resistance is reduced, but thermal budget and fabrication cost increase
Solution Approach 1:
The patent combines the germanium-rich layer formation with the existing oxidation process used for other fabrication purposes. By merging these functions into a single process step, the thermal budget is conserved and no additional high-temperature epitaxial deposition or implantation is required.
Solution Approach 2:
The oxidation process itself provides the thermal energy needed to drive germanium segregation through self-diffusion, eliminating the need for separate high-temperature epitaxial processes that would increase the overall thermal budget.
3Productivity
If device geometry is scaled down to increase functional density, then production efficiency increases, but parasitic resistance at interfaces increases
Solution Approach 1:
The patent applies local quality modification by creating a germanium-rich layer specifically at the contact interface region of the source/drain feature. This localized compositional change reduces interface resistance without requiring overall device enlargement, maintaining high functional density while improving local electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The germanium-rich layer effectively lowers contact resistance, enhancing the performance and reliability of integrated circuits by reducing parasitic effects and avoiding additional fabrication costs and thermal budgets.
Implementation Method 1
The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature
Implementation Method 2
The resistance of such an interface may be due to the quality of the interface as well as the composition of the materials at the interface, and the resistance may increase as the size of the interface decreases
Data Source
AI summary
Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.


