Source/Drain Implantation Profile for Low-Resistance FinFET Junctions
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in reducing channel resistance (Rch) and parasitic resistance (Rp) while minimizing dopant diffusion and P4V cluster formation in source/drain regions, which affects device performance and integration density.
Innovation Solution
A high energy/low dose implantation process is employed to epitaxially grow semiconductor materials and dope them with suitable dopants, forming deep diffusion-less pn junctions and reducing channel length, thereby improving dopant activation and controlling dopant profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional implantation processes are used to dope source/drain regions, then dopant concentration can be increased to reduce channel resistance, but dopant diffusion and P4V cluster formation increase, degrading device performance
Solution Approach 1:
The implantation process is divided into multiple sequential steps with different energies and doses. A first implantation step uses high energy to create deep pn junctions with minimal diffusion, while subsequent steps use lower energies to build up dopant concentration in specific regions. This segmentation allows independent optimization of junction depth and surface concentration, resolving the contradiction between reducing channel resistance and controlling dopant diffusion.
Solution Approach 2:
The patent changes key implantation parameters including energy (from keV to MeV ranges), dose (from 10^12 to 10^15 atoms/cm²), and temperature conditions across different implantation steps. By dynamically adjusting these parameters, the process achieves deep junction formation with sharp profiles while maintaining precise control over dopant distribution, thereby reducing channel resistance without excessive diffusion or P4V cluster formation.
2Manufacturing precision
If multiple implantation processes are used to control dopant profiles, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The multiple implantation steps serve multiple functions simultaneously: the first high-energy step creates deep junctions and prepares the crystal structure, while subsequent steps build dopant concentration and shape the final profile. Each step is optimized to perform its specific function efficiently, and the sequence is designed so that earlier steps enable later steps to achieve their goals with fewer complications, thereby managing complexity while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces channel resistance, parasitic resistance, and minimizes dopant diffusion, enhancing device performance and integration density by accurately defining pn junctions and modulating dopant profiles.
Implementation Method 1
An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material.
Implementation Method 2
After performing the second implantation process, an anneal process is performed on the semiconductor material. The anneal process forms a doped region in the semiconductor fin at an interface between the semiconductor material and the semiconductor fin.
Implementation Method 3
A semiconductor material is deposited in the recess.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.