Source/Drain Contact Formation Using an Inhibitor for Low Resistance
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Solution Overview
Problem
As semiconductor integrated circuits scale down beyond 32 nm, increased source/drain contact resistance and reduced isolation between nearby contacts become significant challenges, necessitating methods to reduce contact resistance and enhance isolation while maintaining process robustness.
Innovation Solution
A process involving the selective deposition of an organic inhibitor on source/drain silicidation exposed in contact holes, followed by the formation of a dielectric liner layer on sidewalls, which avoids vertical etching and increases the source/drain contact area, thereby reducing resistance and improving isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used, then manufacturing process is simpler, but source/drain contact resistance increases and isolation between nearby contacts deteriorates
Solution Approach 1:
An organic inhibitor layer is deposited on the silicide surface before dielectric liner formation. This preliminary action prevents dielectric material from depositing on the silicide, ensuring complete silicide exposure after liner removal without requiring vertical etching, thus reducing contact resistance while maintaining process control
Solution Approach 2:
The organic inhibitor acts as an intermediary layer between the silicide and dielectric liner. It temporarily protects the silicide surface during dielectric deposition, allowing precise control of dielectric liner placement and subsequent removal to expose silicide for low-resistance contacts
2Productivity
If contact hole size is reduced for scaling, then device density increases, but isolation between nearby source/drain contacts deteriorates
Solution Approach 1:
The dielectric liner is applied selectively only on contact hole sidewalls through the organic inhibitor mechanism, not on the silicide surface. This local quality control ensures proper isolation on sidewalls while maintaining complete silicide exposure at the bottom for electrical contact, enabling better isolation in scaled devices
3Area of moving object
If vertical etching of dielectric liner is performed, then contact area is maximized, but process robustness deteriorates due to gate etching
Solution Approach 1:
The organic inhibitor is selectively removed after dielectric liner formation, extracting only the inhibitor layer while leaving the dielectric liner intact on contact hole sidewalls. This extraction approach exposes the silicide surface completely without requiring vertical etching that would affect the gate, maintaining both contact area and process robustness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain contact resistance and maintains robustness by increasing the interfacial area between source/drain contacts and silicide, while avoiding vertical etching of the dielectric liner layer and gate, thus enhancing overall process reliability.
Implementation Method 1
selectively depositing an organic inhibitor on the silicide feature, wherein the organic inhibitor is not deposited on surfaces of the inter-level dielectric layer and the contact etch stop layer
Implementation Method 2
the inhibitor includes an organic film having amphiphilic molecules
Implementation Method 3
selectively depositing a dielectric liner layer on sidewalls and top surfaces of the contact hole, wherein the dielectric liner layer is not deposited on the organic inhibitor
Implementation Method 4
The process includes removing the organic inhibitor
Data Source
AI summary
A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.