Local Source-Drain Isolation in FinFETs to Block Substrate Leakage

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Solution Overview

Problem

The challenge of electrical current leakage from source or drain to the substrate in FinFET or GAA FET devices, leading to power loss and substrate warming, is addressed by using silicon on insulator (SOI) substrates, which are expensive and require local isolations under the source and drain regions.

Innovation Solution

Implementing a local barrier layer below the source and drain regions, created by voids or dopant concentration differences, to prevent current leakage, reducing the need for heavily doped epitaxial layers and minimizing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SOI substrates are used to prevent current leakage, then current leakage is reduced, but manufacturing cost increases

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements local isolation regions with different doping concentrations specifically under the source and drain regions, rather than using uniform SOI substrates across the entire device. This localized approach provides current leakage prevention where most needed while reducing overall manufacturing cost.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping concentration parameter in the isolation region to create a high doping concentration area under the source and drain regions. This parameter change creates an electrical barrier that prevents current leakage without requiring expensive SOI substrates.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If heavily doped epitaxial layers are used to prevent current leakage, then current leakage is reduced, but defect density increases

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoiddefect density
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies heavy doping only in the isolation region under the source and drain, while keeping the epitaxial layers in the active device regions with lower doping concentrations. This localized heavy doping prevents current leakage without introducing excessive defects in the critical transistor regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the doping strategy by creating distinct doping concentration zones: heavily doped isolation region for current leakage prevention, and lightly doped epitaxial layers for high-quality transistor operation. This segmentation allows each region to be optimized for its specific function.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The local barrier layer effectively reduces current leakage, minimizing power loss and substrate warming while lowering the cost and defect rate in semiconductor devices.

Implementation Method 1

forming an isolation region at a bottom portion of the source/drain space... producing a void space between the source/drain epitaxial layer and the substrate

Methodology Applied
Scientific EffectPhysical separation/void region:

Implementation Method 2

Implementing a local barrier layer below the source and drain regions, formed by voids or dopant concentration differences

Methodology Applied
Scientific EffectDopant concentration gradient: Dopants

Data Source

PatentUS12598762B2Methods of manufacturing a semiconductor device with local isolation and a semiconductor device with local isolation
Publication Date: 2026.04.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12598762B2 patent drawing
  • US12598762B2 patent drawing
  • US12598762B2 patent drawing

AI summary

In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.