Source/Drain Isolation Structure to Prevent Epitaxial Merging
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Solution Overview
Problem
As semiconductor devices are scaled down, the small spacing between adjacent transistors can cause epitaxial source/drain features to merge, leading to electrical shorting between transistors, which degrades device performance and can cause failures.
Innovation Solution
The implementation of isolation structures between epitaxially grown source/drain components to prevent unintentional merging, achieved through the formation of sacrificial layers, etching openings, and filling these openings with dielectric materials to create physical and electrical separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is scaled down to increase functional density, then productivity and production efficiency are improved, but the spacing between adjacent transistors decreases causing epitaxial source/drain features to merge and electrical shorting occurs
Solution Approach 1:
The patent divides the continuous epitaxial source/drain region into separate segments by introducing sacrificial liner layers between adjacent source/drain features. These liners act as physical barriers that prevent the merging of epitaxially grown source/drain components, thereby maintaining electrical isolation between adjacent transistors even at scaled dimensions.
Solution Approach 2:
The patent introduces sacrificial liner layers as intermediary structures between adjacent source/drain features. These liners serve as mediator elements that physically separate the source/drain regions during epitaxial growth, preventing direct contact and electrical shorting while allowing the overall device density to increase.
2Area of stationary object
If spacing between adjacent transistors is reduced to increase functional density, then area utilization is improved, but unintentional merging of source/drain features occurs leading to electrical shorting
Solution Approach 1:
The patent applies preliminary action by forming sacrificial liner layers on the substrate before epitaxial growth of the source/drain features. These pre-formed liners establish the separation boundaries in advance, ensuring that even when transistors are closely spaced, the source/drain regions grow independently without merging.
Solution Approach 2:
The patent implements local quality by applying different material properties to different regions: the sacrificial liner layers are placed specifically in the regions between adjacent source/drain features where separation is needed, while the source/drain regions themselves maintain their conductive properties. This localized differentiation ensures separation precision without affecting overall device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The isolation structures effectively prevent electrical shorting between adjacent transistors, improving device yield, reliability, and performance by maintaining the physical separation of source/drain components.
Implementation Method 1
etching openings through the sacrificial layer
Implementation Method 2
filling these openings with dielectric materials
Implementation Method 3
isolation structures effectively prevent electrical shorting between adjacent transistors
Data Source
AI summary
A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.