Source/Drain Contact Isolation Plug for Scaled GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) technology while maintaining effective isolation between source/drain contacts, which affects device performance and efficiency.
Innovation Solution
The method involves forming an isolation plug after the source/drain contacts are enlarged, using a mask layer to separate adjacent source/drain contacts, and employing a low-aspect-ratio opening for filling the isolation plug, allowing for improved conductivity and reduced plug size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but device performance and precision patterning become more difficult to maintain
Solution Approach 1:
The patent applies multi-patterning processes that divide the patterning operation into multiple sequential steps, where each step creates a portion of the final pattern. This segmentation allows achieving higher precision at scaled dimensions by breaking down the complex single-step patterning into manageable stages, thereby maintaining manufacturing precision while enabling continued scaling for improved productivity.
Solution Approach 2:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed in advance before the final pattern transfer. These preliminary structures serve as templates that guide subsequent etching steps, ensuring precise feature formation at reduced geometries. This preliminary action enables accurate patterning to be achieved even as feature sizes decrease, maintaining precision while allowing continued scaling for higher productivity.
2Reliability
If GAA transistor structures are formed with precise patterning, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent implements nested structures where spacer layers are formed around mandrel structures, and subsequent patterns are defined relative to these nested elements. The multi-layer spacer and mandrel configuration creates a nested arrangement that enables precise GAA transistor patterning through self-aligned processes, improving device performance while the modular nested approach helps manage fabrication complexity by creating repeatable pattern units.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional GAA transistor structures with vertical channels surrounded by gates on multiple sides. This dimensional change enables superior device performance through enhanced gate control, while the use of self-aligned spacer formation and sequential patterning steps provides a systematic approach to managing the increased fabrication complexity inherent in three-dimensional structure creation.
3Reliability
If source/drain contacts are enlarged after formation, then electrical connection is improved, but additional processing steps are required
Solution Approach 1:
The patent forms isolation plugs and contact structures in a sequential manner where preliminary isolation regions are defined before contact formation. The contact enlargement is achieved through controlled deposition and etching steps that build upon previously formed structures, improving electrical connection reliability while the sequential approach integrates the enlargement process into the existing fabrication flow, managing overall processing complexity.
Solution Approach 2:
The patent introduces isolation plugs as intermediary structures that mediate between the source/drain contacts and the substrate. These plugs serve multiple functions: providing electrical isolation, enabling contact enlargement through controlled deposition, and facilitating subsequent processing steps. The intermediary isolation plug structure allows contact size optimization for improved electrical connection while the modular design helps manage fabrication complexity by creating distinct, manageable processing stages.
Data Source
AI summary
A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.


